{"id":{"repo_id":"vt","oai_identifier":"oai:vtechworks.lib.vt.edu:10919/76003"},"canonical_url":"https://search.dev.ndltd.org/etd/vt/oai:vtechworks.lib.vt.edu:10919/76003","repository":{"repo_id":"vt","name":"Virginia Tech","base_url":"https://vtechworks.lib.vt.edu/oai/request"},"display":{"title":"Fault tolerant clocking system","abstract":"The distributions of synchronized clock signals to all elements of a computing system is very important. Fletcher's clock patent is a good solution to this problem. The difficulty with implementation is the tremendous number of interconnections among different clock elements. Two methods are proposed to reduce the number of interconnectons without loss of synchronization and fault-tolerant capability. An mth order clock is a circuit consisting of (3f+1) ** (2** (m-1)) (m-1)th order clocks. Fletcher's clock patent is a 0th order clock. Starting with 0th order clocks, an mth order clock circuit can be built systematically. An mth order clock circuit can generate (3f+1)**(2**m) synchronized clock signals with (m + 1) (3f+ 1) ** ( 2**m) interconnections instead of (3f+1) ** (2*2**m) • Its fault-tolerant capability is also considered. Another type of connection is called Iterative Type, which is further classified into Cascaded Type, Scattering Type and 2-dimensional Type. Each type has its own characteristics.","abstract_html":"The distributions of synchronized clock signals to all elements of a computing system is very important. Fletcher's clock patent is a good solution to this problem. The difficulty with implementation is the tremendous number of interconnections among different clock elements. Two methods are proposed to reduce the number of interconnectons without loss of synchronization and fault-tolerant capability. An mth order clock is a circuit consisting of (3f+1) ** (2** (m-1)) (m-1)th order clocks. Fletcher's clock patent is a 0th order clock. Starting with 0th order clocks, an mth order clock circuit can be built systematically. An mth order clock circuit can generate (3f+1)**(2**m) synchronized clock signals with (m + 1) (3f+ 1) ** ( 2**m) interconnections instead of (3f+1) ** (2*2**m) • Its fault-tolerant capability is also considered. Another type of connection is called Iterative Type, which is further classified into Cascaded Type, Scattering Type and 2-dimensional Type. Each type has its own characteristics.","abstract_has_math":false,"creators":["Fan, Tzu-I Jonathan"],"institution":"Virginia Polytechnic Institute and State University","degree_name":"Master of Science","degree_level":"masters","degree_discipline":"Electrical Engineering","degree_department":"Electrical Engineering","school":null,"contributors":[],"advisors":[],"committee_chairs":[],"committee_members":[],"year":1978,"date_issued":"1978","date_published":"1978","updated_at":"2026-07-22T22:19:06Z","subjects":[],"languages":["en"],"rights":["In Copyright"],"rights_urls":["http://rightsstatements.org/vocab/InC/1.0/"],"identifier_entries":[]},"links":{"outbound_url":"http://hdl.handle.net/10919/76003","outbound_label":"Handle","outbound_source":"dc:identifier.uri"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor.department","label":"Department","values":["Electrical Engineering"]},{"key":"dc:creator","label":"Author","values":["Fan, Tzu-I Jonathan"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date.accessioned","label":"Dc Date Accessioned","values":["2017-03-09T21:35:10Z"]},{"key":"dc:date.available","label":"Dc Date Available","values":["2017-03-09T21:35:10Z"]},{"key":"dc:date.issued","label":"Date","values":["1978"]},{"key":"dc:publisher","label":"Institution","values":["Virginia Polytechnic Institute and State University"]},{"key":"dc:type","label":"Dc Type","values":["Thesis"]},{"key":"dc:type.dcmitype","label":"Dc Type Dcmitype","values":["Text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical Engineering"]},{"key":"thesis:degree_level","label":"Degree Level","values":["masters"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Master of Science"]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["Virginia Polytechnic Institute and State University"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language.iso","label":"Language (ISO)","values":["en"]},{"key":"dc:rights","label":"Dc Rights","values":["In Copyright"]},{"key":"dc:rights.uri","label":"Rights URI","values":["http://rightsstatements.org/vocab/InC/1.0/"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier.uri","label":"Identifier URI","values":["http://hdl.handle.net/10919/76003"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description.abstract","label":"Abstract","values":["The distributions of synchronized clock signals to all elements of a computing system is very important. Fletcher's clock patent is a good solution to this problem. The difficulty with implementation is the tremendous number of interconnections among different clock elements. Two methods are proposed to reduce the number of interconnectons without loss of synchronization and fault-tolerant capability. An mth order clock is a circuit consisting of (3f+1) ** (2** (m-1)) (m-1)th order clocks. Fletcher's clock patent is a 0th order clock. Starting with 0th order clocks, an mth order clock circuit can be built systematically. An mth order clock circuit can generate (3f+1)**(2**m) synchronized clock signals with (m + 1) (3f+ 1) ** ( 2**m) interconnections instead of (3f+1) ** (2*2**m) • Its fault-tolerant capability is also considered. Another type of connection is called Iterative Type, which is further classified into Cascaded Type, Scattering Type and 2-dimensional Type. Each type has its own characteristics."]},{"key":"dc:description.degree","label":"Dc Description Degree","values":["Master of Science"]},{"key":"dc:format.mimetype","label":"Dc Format Mimetype","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["Fault tolerant clocking system"]}]}],"canonical_facts":{"dc:contributor.department":["Electrical Engineering"],"dc:creator":["Fan, Tzu-I Jonathan"],"dc:date.accessioned":["2017-03-09T21:35:10Z"],"dc:date.available":["2017-03-09T21:35:10Z"],"dc:date.issued":["1978"],"dc:description.abstract":["The distributions of synchronized clock signals to all elements of a computing system is very important. Fletcher's clock patent is a good solution to this problem. The difficulty with implementation is the tremendous number of interconnections among different clock elements. Two methods are proposed to reduce the number of interconnectons without loss of synchronization and fault-tolerant capability. An mth order clock is a circuit consisting of (3f+1) ** (2** (m-1)) (m-1)th order clocks. Fletcher's clock patent is a 0th order clock. Starting with 0th order clocks, an mth order clock circuit can be built systematically. An mth order clock circuit can generate (3f+1)**(2**m) synchronized clock signals with (m + 1) (3f+ 1) ** ( 2**m) interconnections instead of (3f+1) ** (2*2**m) • Its fault-tolerant capability is also considered. Another type of connection is called Iterative Type, which is further classified into Cascaded Type, Scattering Type and 2-dimensional Type. Each type has its own characteristics."],"dc:description.degree":["Master of Science"],"dc:format.mimetype":["application/pdf"],"dc:identifier.uri":["http://hdl.handle.net/10919/76003"],"dc:language.iso":["en"],"dc:publisher":["Virginia Polytechnic Institute and State University"],"dc:rights":["In Copyright"],"dc:rights.uri":["http://rightsstatements.org/vocab/InC/1.0/"],"dc:title":["Fault tolerant clocking system"],"dc:type":["Thesis"],"dc:type.dcmitype":["Text"],"thesis:degree_discipline":["Electrical Engineering"],"thesis:degree_level":["masters"],"thesis:degree_name":["Master of Science"],"thesis:institution_name":["Virginia Polytechnic Institute and State University"]},"updated_at":"2026-07-22T22:19:06Z"}