Abstract
dc:description.abstractBitstream generation has traditionally been the single part of the FPGA design flow that has not been openly reproduced. This work enables bitstream generation for "limited" resources without reverse-engineering or violating End-User License Agreement terms. Two use cases in particular have motivated this work--embedded bitstream generation and fast bitstream generation for small changes in design--both of which are not feasible with the Xilinx's bitstream generation tool. The approach is to first define a set of primitives which can implement an arbitrary digital design and create a library of micro-bitstreams of the primitives. An input design is then mapped to the set of primitives and a bitstream for the design is generated by merging the corresponding micro-bitstreams. This work uses architectural primitives. Initial support is limited to the Virtex-5 and Virtex-7 family of FPGAs from Xilinx, but it can be extended to other Xilinx architectures. Nearly all routing resources in the device, as well as the most common logic resources are supported by this work.
Degree
thesis:*- Name thesis:degree_name
- Master of Science
- Level thesis:degree_level
- masters
- Discipline thesis:degree_discipline
- Computer Engineering
- Department dc:contributor.department
- Electrical and Computer Engineering
- Grantor dc:publisher
- Virginia Tech
- Year dc:date.issued
- 2013
Author and committee
dc:creator, dc:contributor.*- Author dc:creator
-
- Soni, Ritesh K.
- Chair dc:contributor.committeechair
-
- Athanas, Peter M.
- Committee members dc:contributor.committeemember
-
- Jones, Mark T.
- Schaumont, Patrick R.
Subjects
dc:subject × 4Rights
dc:rights- Statement dc:rights
-
- In Copyright
- Licence dc:rights.uri
Identifiers
dc:identifier.*- Dc Identifier Other
- vt_gsexam:1612
- OAI identifier oai:identifier
- oai:vtechworks.lib.vt.edu:10919/51836