{"id":{"repo_id":"vt","oai_identifier":"oai:vtechworks.lib.vt.edu:10919/51836"},"canonical_url":"https://search.dev.ndltd.org/etd/vt/oai:vtechworks.lib.vt.edu:10919/51836","repository":{"repo_id":"vt","name":"Virginia Tech","base_url":"https://vtechworks.lib.vt.edu/oai/request"},"display":{"title":"Open-Source Bitstream Generation for FPGAs","abstract":"Bitstream generation has traditionally been the single part of the FPGA design flow that has not been openly reproduced. This work enables bitstream generation for \"limited\" resources without reverse-engineering or violating End-User License Agreement terms. Two use cases in particular have motivated this work--embedded bitstream generation and fast bitstream generation for small changes in design--both of which are not feasible with the Xilinx's bitstream generation tool. The approach is to first define a set of primitives which can implement an arbitrary digital design and create a library of micro-bitstreams of the primitives. An input design is then mapped to the set of primitives and a bitstream for the design is generated by merging the corresponding micro-bitstreams. This work uses architectural primitives. Initial support is limited to the Virtex-5 and Virtex-7 family of FPGAs from Xilinx, but it can be extended to other Xilinx architectures. Nearly all routing resources in the device, as well as the most common logic resources are supported by this work.","abstract_html":"Bitstream generation has traditionally been the single part of the FPGA design flow that has not been openly reproduced. This work enables bitstream generation for "limited" resources without reverse-engineering or violating End-User License Agreement terms. Two use cases in particular have motivated this work--embedded bitstream generation and fast bitstream generation for small changes in design--both of which are not feasible with the Xilinx's bitstream generation tool. The approach is to first define a set of primitives which can implement an arbitrary digital design and create a library of micro-bitstreams of the primitives. An input design is then mapped to the set of primitives and a bitstream for the design is generated by merging the corresponding micro-bitstreams. This work uses architectural primitives. Initial support is limited to the Virtex-5 and Virtex-7 family of FPGAs from Xilinx, but it can be extended to other Xilinx architectures. Nearly all routing resources in the device, as well as the most common logic resources are supported by this work.","abstract_has_math":false,"creators":["Soni, Ritesh K."],"institution":"Virginia Tech","degree_name":"Master of Science","degree_level":"masters","degree_discipline":"Computer Engineering","degree_department":"Electrical and Computer Engineering","school":null,"contributors":[],"advisors":[],"committee_chairs":["Athanas, Peter M."],"committee_members":["Jones, Mark T.","Schaumont, Patrick R."],"year":2013,"date_issued":"2013-08-30","date_published":"2013-08-30","updated_at":"2026-07-22T22:18:46Z","subjects":["Field programmable gate arrays","bitstream","low-level assembly","open-source"],"languages":[],"rights":["In Copyright"],"rights_urls":["http://rightsstatements.org/vocab/InC/1.0/"],"identifier_entries":[{"key":"dc:identifier.other","label":"Dc Identifier Other","values":["vt_gsexam:1612"],"render_values":[{"text":"vt_gsexam:1612","href":null,"code":true}]}]},"links":{"outbound_url":"http://hdl.handle.net/10919/51836","outbound_label":"Handle","outbound_source":"dc:identifier.uri"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor.committeechair","label":"Committee Chair","values":["Athanas, Peter M."]},{"key":"dc:contributor.committeemember","label":"Committee Member","values":["Jones, Mark T.","Schaumont, Patrick R."]},{"key":"dc:contributor.department","label":"Department","values":["Electrical and Computer Engineering"]},{"key":"dc:creator","label":"Author","values":["Soni, Ritesh K."]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date.accessioned","label":"Dc Date Accessioned","values":["2015-04-28T08:02:38Z"]},{"key":"dc:date.available","label":"Dc Date Available","values":["2015-04-28T08:02:38Z"]},{"key":"dc:date.issued","label":"Date","values":["2013-08-30"]},{"key":"dc:publisher","label":"Institution","values":["Virginia Tech"]},{"key":"dc:type","label":"Dc Type","values":["Thesis"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Computer Engineering"]},{"key":"thesis:degree_level","label":"Degree Level","values":["masters"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Master of Science"]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["Virginia Polytechnic Institute and State University"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Field programmable gate arrays","bitstream","low-level assembly","open-source"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:rights","label":"Dc Rights","values":["In Copyright"]},{"key":"dc:rights.uri","label":"Rights URI","values":["http://rightsstatements.org/vocab/InC/1.0/"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier.other","label":"Dc Identifier Other","values":["vt_gsexam:1612"]},{"key":"dc:identifier.uri","label":"Identifier URI","values":["http://hdl.handle.net/10919/51836"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description.abstract","label":"Abstract","values":["Bitstream generation has traditionally been the single part of the FPGA design flow that has not been openly reproduced. This work enables bitstream generation for \"limited\" resources without reverse-engineering or violating End-User License Agreement terms. Two use cases in particular have motivated this work--embedded bitstream generation and fast bitstream generation for small changes in design--both of which are not feasible with the Xilinx's bitstream generation tool. The approach is to first define a set of primitives which can implement an arbitrary digital design and create a library of micro-bitstreams of the primitives. An input design is then mapped to the set of primitives and a bitstream for the design is generated by merging the corresponding micro-bitstreams. This work uses architectural primitives. Initial support is limited to the Virtex-5 and Virtex-7 family of FPGAs from Xilinx, but it can be extended to other Xilinx architectures. Nearly all routing resources in the device, as well as the most common logic resources are supported by this work."]},{"key":"dc:description.degree","label":"Dc Description Degree","values":["Master of Science"]},{"key":"dc:format.medium","label":"Dc Format Medium","values":["ETD"]},{"key":"dc:title","label":"Title","values":["Open-Source Bitstream Generation for FPGAs"]}]}],"canonical_facts":{"dc:contributor.committeechair":["Athanas, Peter M."],"dc:contributor.committeemember":["Jones, Mark T.","Schaumont, Patrick R."],"dc:contributor.department":["Electrical and Computer Engineering"],"dc:creator":["Soni, Ritesh K."],"dc:date.accessioned":["2015-04-28T08:02:38Z"],"dc:date.available":["2015-04-28T08:02:38Z"],"dc:date.issued":["2013-08-30"],"dc:description.abstract":["Bitstream generation has traditionally been the single part of the FPGA design flow that has not been openly reproduced. This work enables bitstream generation for \"limited\" resources without reverse-engineering or violating End-User License Agreement terms. Two use cases in particular have motivated this work--embedded bitstream generation and fast bitstream generation for small changes in design--both of which are not feasible with the Xilinx's bitstream generation tool. The approach is to first define a set of primitives which can implement an arbitrary digital design and create a library of micro-bitstreams of the primitives. An input design is then mapped to the set of primitives and a bitstream for the design is generated by merging the corresponding micro-bitstreams. This work uses architectural primitives. Initial support is limited to the Virtex-5 and Virtex-7 family of FPGAs from Xilinx, but it can be extended to other Xilinx architectures. Nearly all routing resources in the device, as well as the most common logic resources are supported by this work."],"dc:description.degree":["Master of Science"],"dc:format.medium":["ETD"],"dc:identifier.other":["vt_gsexam:1612"],"dc:identifier.uri":["http://hdl.handle.net/10919/51836"],"dc:publisher":["Virginia Tech"],"dc:rights":["In Copyright"],"dc:rights.uri":["http://rightsstatements.org/vocab/InC/1.0/"],"dc:subject":["Field programmable gate arrays","bitstream","low-level assembly","open-source"],"dc:title":["Open-Source Bitstream Generation for FPGAs"],"dc:type":["Thesis"],"thesis:degree_discipline":["Computer Engineering"],"thesis:degree_level":["masters"],"thesis:degree_name":["Master of Science"],"thesis:institution_name":["Virginia Polytechnic Institute and State University"]},"updated_at":"2026-07-22T22:18:46Z"}