Behavioral delay fault modeling and test generation

As the speed of operation of VLSI devices has increased, delay fault testing has become a more important factor in VLSI testing. Due to the large number of gates in a VLSI circuit, the gate level test generation methodologies may become infeasible for delay test generation. In this work, a new behavioral delay fault model that aims at simplifying the delay test generation problem for digital circuits is presented. The model is defined using VHDL. It is shown that each defined behavioral level delay fault can be mapped to a gate level equivalent fault and/or physical failure. A systematic way of representing a behavioral model in terms of a data flow graph is presented. A behavioral level input-output path is defined and a strategy to generate tests for delay faults along a behavioral path is presented. It is then shown that tests developed from the behavioral model can test a gate level equivalent circuit for path delay faults.

Name thesis:degree_name

Master of Science

Level thesis:degree_level

masters

Discipline thesis:degree_discipline

Electrical Engineering

Department dc:contributor.department

Electrical Engineering

Grantor dc:publisher

Virginia Tech

Year dc:date.issued

1994

Author dc:creator

• Joshi, Anand Mukund

Chair dc:contributor.committeechair

• Armstrong, James R.

Committee members dc:contributor.committeemember

• Cyre, Walling R.
• Gray, Festus Gail

Statement dc:rights

• In Copyright

Licence dc:rights.uri

• http://rightsstatements.org/vocab/InC/1.0/

Language dc:language.iso

en

Dc Identifier Other

etd-07292009-090436

OAI identifier oai:identifier

oai:vtechworks.lib.vt.edu:10919/43996