{"id":{"repo_id":"vt","oai_identifier":"oai:vtechworks.lib.vt.edu:10919/43996"},"canonical_url":"https://search.dev.ndltd.org/etd/vt/oai:vtechworks.lib.vt.edu:10919/43996","repository":{"repo_id":"vt","name":"Virginia Tech","base_url":"https://vtechworks.lib.vt.edu/oai/request"},"display":{"title":"Behavioral delay fault modeling and test generation","abstract":"As the speed of operation of VLSI devices has increased, delay fault testing has become a more important factor in VLSI testing. Due to the large number of gates in a VLSI circuit, the gate level test generation methodologies may become infeasible for delay test generation. In this work, a new behavioral delay fault model that aims at simplifying the delay test generation problem for digital circuits is presented. The model is defined using VHDL. It is shown that each defined behavioral level delay fault can be mapped to a gate level equivalent fault and/or physical failure. A systematic way of representing a behavioral model in terms of a data flow graph is presented. A behavioral level input-output path is defined and a strategy to generate tests for delay faults along a behavioral path is presented. It is then shown that tests developed from the behavioral model can test a gate level equivalent circuit for path delay faults.","abstract_html":"As the speed of operation of VLSI devices has increased, delay fault testing has become a more important factor in VLSI testing. Due to the large number of gates in a VLSI circuit, the gate level test generation methodologies may become infeasible for delay test generation. In this work, a new behavioral delay fault model that aims at simplifying the delay test generation problem for digital circuits is presented. The model is defined using VHDL. It is shown that each defined behavioral level delay fault can be mapped to a gate level equivalent fault and/or physical failure. A systematic way of representing a behavioral model in terms of a data flow graph is presented. A behavioral level input-output path is defined and a strategy to generate tests for delay faults along a behavioral path is presented. It is then shown that tests developed from the behavioral model can test a gate level equivalent circuit for path delay faults.","abstract_has_math":false,"creators":["Joshi, Anand Mukund"],"institution":"Virginia Tech","degree_name":"Master of Science","degree_level":"masters","degree_discipline":"Electrical Engineering","degree_department":"Electrical Engineering","school":null,"contributors":[],"advisors":[],"committee_chairs":["Armstrong, James R."],"committee_members":["Cyre, Walling R.","Gray, Festus Gail"],"year":1994,"date_issued":"1994-05-05","date_published":"1994-05-05","updated_at":"2026-07-22T22:18:55Z","subjects":[],"languages":["en"],"rights":["In Copyright"],"rights_urls":["http://rightsstatements.org/vocab/InC/1.0/"],"identifier_entries":[{"key":"dc:identifier.other","label":"Dc Identifier Other","values":["etd-07292009-090436"],"render_values":[{"text":"etd-07292009-090436","href":null,"code":true}]}]},"links":{"outbound_url":"http://hdl.handle.net/10919/43996","outbound_label":"Handle","outbound_source":"dc:identifier.uri"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor.committeechair","label":"Committee Chair","values":["Armstrong, James R."]},{"key":"dc:contributor.committeemember","label":"Committee Member","values":["Cyre, Walling R.","Gray, Festus Gail"]},{"key":"dc:contributor.department","label":"Department","values":["Electrical Engineering"]},{"key":"dc:creator","label":"Author","values":["Joshi, Anand Mukund"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date.accessioned","label":"Dc Date Accessioned","values":["2014-03-14T21:41:36Z"]},{"key":"dc:date.available","label":"Dc Date Available","values":["2014-03-14T21:41:36Z","2009-07-29"]},{"key":"dc:date.issued","label":"Date","values":["1994-05-05"]},{"key":"dc:publisher","label":"Institution","values":["Virginia Tech"]},{"key":"dc:type","label":"Dc Type","values":["Thesis"]},{"key":"dc:type.dcmitype","label":"Dc Type Dcmitype","values":["Text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical Engineering"]},{"key":"thesis:degree_level","label":"Degree Level","values":["masters"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Master of Science"]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["Virginia Polytechnic Institute and State University"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language.iso","label":"Language (ISO)","values":["en"]},{"key":"dc:rights","label":"Dc Rights","values":["In Copyright"]},{"key":"dc:rights.uri","label":"Rights URI","values":["http://rightsstatements.org/vocab/InC/1.0/"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier.other","label":"Dc Identifier Other","values":["etd-07292009-090436"]},{"key":"dc:identifier.uri","label":"Identifier URI","values":["http://hdl.handle.net/10919/43996"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description.abstract","label":"Abstract","values":["As the speed of operation of VLSI devices has increased, delay fault testing has become a more important factor in VLSI testing. Due to the large number of gates in a VLSI circuit, the gate level test generation methodologies may become infeasible for delay test generation. In this work, a new behavioral delay fault model that aims at simplifying the delay test generation problem for digital circuits is presented. The model is defined using VHDL. It is shown that each defined behavioral level delay fault can be mapped to a gate level equivalent fault and/or physical failure. A systematic way of representing a behavioral model in terms of a data flow graph is presented. A behavioral level input-output path is defined and a strategy to generate tests for delay faults along a behavioral path is presented. It is then shown that tests developed from the behavioral model can test a gate level equivalent circuit for path delay faults."]},{"key":"dc:description.degree","label":"Dc Description Degree","values":["Master of Science"]},{"key":"dc:format.medium","label":"Dc Format Medium","values":["BTD"]},{"key":"dc:format.mimetype","label":"Dc Format Mimetype","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["Behavioral delay fault modeling and test generation"]}]}],"canonical_facts":{"dc:contributor.committeechair":["Armstrong, James R."],"dc:contributor.committeemember":["Cyre, Walling R.","Gray, Festus Gail"],"dc:contributor.department":["Electrical Engineering"],"dc:creator":["Joshi, Anand Mukund"],"dc:date.accessioned":["2014-03-14T21:41:36Z"],"dc:date.available":["2014-03-14T21:41:36Z","2009-07-29"],"dc:date.issued":["1994-05-05"],"dc:description.abstract":["As the speed of operation of VLSI devices has increased, delay fault testing has become a more important factor in VLSI testing. Due to the large number of gates in a VLSI circuit, the gate level test generation methodologies may become infeasible for delay test generation. In this work, a new behavioral delay fault model that aims at simplifying the delay test generation problem for digital circuits is presented. The model is defined using VHDL. It is shown that each defined behavioral level delay fault can be mapped to a gate level equivalent fault and/or physical failure. A systematic way of representing a behavioral model in terms of a data flow graph is presented. A behavioral level input-output path is defined and a strategy to generate tests for delay faults along a behavioral path is presented. It is then shown that tests developed from the behavioral model can test a gate level equivalent circuit for path delay faults."],"dc:description.degree":["Master of Science"],"dc:format.medium":["BTD"],"dc:format.mimetype":["application/pdf"],"dc:identifier.other":["etd-07292009-090436"],"dc:identifier.uri":["http://hdl.handle.net/10919/43996"],"dc:language.iso":["en"],"dc:publisher":["Virginia Tech"],"dc:rights":["In Copyright"],"dc:rights.uri":["http://rightsstatements.org/vocab/InC/1.0/"],"dc:title":["Behavioral delay fault modeling and test generation"],"dc:type":["Thesis"],"dc:type.dcmitype":["Text"],"thesis:degree_discipline":["Electrical Engineering"],"thesis:degree_level":["masters"],"thesis:degree_name":["Master of Science"],"thesis:institution_name":["Virginia Polytechnic Institute and State University"]},"updated_at":"2026-07-22T22:18:55Z"}