Abstract
dc:description.abstractThis thesis describes the development of a graphical CAD tool for VHDL model development. The tool was developed for the X Windows environment. The graphical representation used is the process model graph [1,4]. The process model graph is input interactively and the tool generates the corresponding VHDL code. The design style is restricted to behavioral models. A new scheme was formulated for the development and use of reusable code in the form of primitives. A default set of primitives as presented in [5] was also developed. The tool can also attach to any VHDL analyzer available on the system and analyze the developed code. This tool is designed for use by system modelers and should simplify the process of model development, thus improving productivity.
Degree
thesis:*- Name thesis:degree_name
- Master of Science
- Level thesis:degree_level
- masters
- Discipline thesis:degree_discipline
- Electrical Engineering
- Department dc:contributor.department
- Electrical Engineering
- Grantor dc:publisher
- Virginia Tech
- Year dc:date.issued
- 1990
Author and committee
dc:creator, dc:contributor.*- Author dc:creator
-
- Singh, Balraj
Rights
dc:rights- Statement dc:rights
-
- In Copyright
- Licence dc:rights.uri
- Language dc:language.iso
- en
Identifiers
dc:identifier.*- Dc Identifier Other
- etd-03242009-040819
- OAI identifier oai:identifier
- oai:vtechworks.lib.vt.edu:10919/41781