{"id":{"repo_id":"vt","oai_identifier":"oai:vtechworks.lib.vt.edu:10919/41781"},"canonical_url":"https://search.dev.ndltd.org/etd/vt/oai:vtechworks.lib.vt.edu:10919/41781","repository":{"repo_id":"vt","name":"Virginia Tech","base_url":"https://vtechworks.lib.vt.edu/oai/request"},"display":{"title":"A parametrized CAD tool for VHDL model development with X Windows","abstract":"This thesis describes the development of a graphical CAD tool for VHDL model development. The tool was developed for the X Windows environment. The graphical representation used is the process model graph [1,4]. The process model graph is input interactively and the tool generates the corresponding VHDL code. The design style is restricted to behavioral models. A new scheme was formulated for the development and use of reusable code in the form of primitives. A default set of primitives as presented in [5] was also developed. The tool can also attach to any VHDL analyzer available on the system and analyze the developed code. This tool is designed for use by system modelers and should simplify the process of model development, thus improving productivity.","abstract_html":"This thesis describes the development of a graphical CAD tool for VHDL model development. The tool was developed for the X Windows environment. The graphical representation used is the process model graph [1,4]. The process model graph is input interactively and the tool generates the corresponding VHDL code. The design style is restricted to behavioral models. A new scheme was formulated for the development and use of reusable code in the form of primitives. A default set of primitives as presented in [5] was also developed. The tool can also attach to any VHDL analyzer available on the system and analyze the developed code. This tool is designed for use by system modelers and should simplify the process of model development, thus improving productivity.","abstract_has_math":false,"creators":["Singh, Balraj"],"institution":"Virginia Tech","degree_name":"Master of Science","degree_level":"masters","degree_discipline":"Electrical Engineering","degree_department":"Electrical Engineering","school":null,"contributors":[],"advisors":[],"committee_chairs":[],"committee_members":[],"year":1990,"date_issued":"1990","date_published":"1990","updated_at":"2026-07-22T22:20:07Z","subjects":[],"languages":["en"],"rights":["In Copyright"],"rights_urls":["http://rightsstatements.org/vocab/InC/1.0/"],"identifier_entries":[{"key":"dc:identifier.other","label":"Dc Identifier Other","values":["etd-03242009-040819"],"render_values":[{"text":"etd-03242009-040819","href":null,"code":true}]}]},"links":{"outbound_url":"http://hdl.handle.net/10919/41781","outbound_label":"Handle","outbound_source":"dc:identifier.uri"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor.department","label":"Department","values":["Electrical Engineering"]},{"key":"dc:creator","label":"Author","values":["Singh, Balraj"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date.accessioned","label":"Dc Date Accessioned","values":["2014-03-14T21:32:21Z"]},{"key":"dc:date.available","label":"Dc Date Available","values":["2014-03-14T21:32:21Z","2009-03-24"]},{"key":"dc:date.issued","label":"Date","values":["1990"]},{"key":"dc:publisher","label":"Institution","values":["Virginia Tech"]},{"key":"dc:type","label":"Dc Type","values":["Thesis"]},{"key":"dc:type.dcmitype","label":"Dc Type Dcmitype","values":["Text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical Engineering"]},{"key":"thesis:degree_level","label":"Degree Level","values":["masters"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Master of Science"]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["Virginia Polytechnic Institute and State University"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language.iso","label":"Language (ISO)","values":["en"]},{"key":"dc:rights","label":"Dc Rights","values":["In Copyright"]},{"key":"dc:rights.uri","label":"Rights URI","values":["http://rightsstatements.org/vocab/InC/1.0/"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier.other","label":"Dc Identifier Other","values":["etd-03242009-040819"]},{"key":"dc:identifier.uri","label":"Identifier URI","values":["http://hdl.handle.net/10919/41781"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description.abstract","label":"Abstract","values":["This thesis describes the development of a graphical CAD tool for VHDL model development. The tool was developed for the X Windows environment. The graphical representation used is the process model graph [1,4]. The process model graph is input interactively and the tool generates the corresponding VHDL code. The design style is restricted to behavioral models. A new scheme was formulated for the development and use of reusable code in the form of primitives. A default set of primitives as presented in [5] was also developed. The tool can also attach to any VHDL analyzer available on the system and analyze the developed code. This tool is designed for use by system modelers and should simplify the process of model development, thus improving productivity."]},{"key":"dc:description.degree","label":"Dc Description Degree","values":["Master of Science"]},{"key":"dc:format.medium","label":"Dc Format Medium","values":["BTD"]},{"key":"dc:format.mimetype","label":"Dc Format Mimetype","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["A parametrized CAD tool for VHDL model development with X Windows"]}]}],"canonical_facts":{"dc:contributor.department":["Electrical Engineering"],"dc:creator":["Singh, Balraj"],"dc:date.accessioned":["2014-03-14T21:32:21Z"],"dc:date.available":["2014-03-14T21:32:21Z","2009-03-24"],"dc:date.issued":["1990"],"dc:description.abstract":["This thesis describes the development of a graphical CAD tool for VHDL model development. The tool was developed for the X Windows environment. The graphical representation used is the process model graph [1,4]. The process model graph is input interactively and the tool generates the corresponding VHDL code. The design style is restricted to behavioral models. A new scheme was formulated for the development and use of reusable code in the form of primitives. A default set of primitives as presented in [5] was also developed. The tool can also attach to any VHDL analyzer available on the system and analyze the developed code. This tool is designed for use by system modelers and should simplify the process of model development, thus improving productivity."],"dc:description.degree":["Master of Science"],"dc:format.medium":["BTD"],"dc:format.mimetype":["application/pdf"],"dc:identifier.other":["etd-03242009-040819"],"dc:identifier.uri":["http://hdl.handle.net/10919/41781"],"dc:language.iso":["en"],"dc:publisher":["Virginia Tech"],"dc:rights":["In Copyright"],"dc:rights.uri":["http://rightsstatements.org/vocab/InC/1.0/"],"dc:title":["A parametrized CAD tool for VHDL model development with X Windows"],"dc:type":["Thesis"],"dc:type.dcmitype":["Text"],"thesis:degree_discipline":["Electrical Engineering"],"thesis:degree_level":["masters"],"thesis:degree_name":["Master of Science"],"thesis:institution_name":["Virginia Polytechnic Institute and State University"]},"updated_at":"2026-07-22T22:20:07Z"}