An FPGA-Based Multiuser Receiver Employing Parallel Interference Cancellation

Research efforts have shown that capacity in a DS/CDMA cellular system can be increased through the use of digital signal processing techniques that exploit the nature of the multiple access interference (MAI). By jointly demodulating the users in the system, this interference can be characterized and reduced thus decreasing the overall probability of error in the system. Numerous multiuser structures exist, each with varying degrees of complexity and performance. However, the size and complexity of these structures is large relative to a conventional receiver. This effort demonstrates a practical approach to implementing parallel interference cancellation applied to DBPSK DS/CDMA on an FPGA-based configurable computing platform. The system presented acquires, tracks, cancels, and demodulates four users independently and performs various levels of interference cancellation. The performance gain of the receiver in a four-user environment under various levels of noise and cancellation are presented.

Name thesis:degree_name

Master of Science

Level thesis:degree_level

masters

Discipline thesis:degree_discipline

Electrical and Computer Engineering

Department dc:contributor.department

Electrical and Computer Engineering

Grantor dc:publisher

Virginia Tech

Year dc:date.issued

1998

Author dc:creator

• Swanchara, Steven F.

Chair dc:contributor.committeechair

• Reed, Jeffrey H.

Committee members dc:contributor.committeemember

• Woerner, Brian D.
• Athanas, Peter M.

• Field programmable gate arrays
• CDMA
• Multiuser Receiver
• Interference Cancellation
• Configurable Computing

Statement dc:rights

• In Copyright

Licence dc:rights.uri

• http://rightsstatements.org/vocab/InC/1.0/

Dc Identifier Other

etd-81598-221016

OAI identifier oai:identifier

oai:vtechworks.lib.vt.edu:10919/36983