BitMaT - Bitstream Manipulation Tool for Xilinx FPGAs

With the introduction of partially reconfigurable FPGAs, we are now able to perform dynamic changes to hardware running on an FPGA without halting the operation of the design. Module based partial reconfiguration allows the hardware designer to create multiple hardware modules that perform different tasks and swap them in and out of designated dynamic regions on an FPGA. However, the current mainstream partial reconfiguration flow provides a limited and inefficient approach that requires a strict set of guidelines to be met. This thesis introduces BitMaT, a tool that provides the low-level bitstream manipulation as a member tool of an alternative, automated, modular partial reconfiguration flow.

Name thesis:degree_name

Master of Science

Level thesis:degree_level

masters

Discipline thesis:degree_discipline

Electrical and Computer Engineering

Department dc:contributor.department

Electrical and Computer Engineering

Grantor dc:publisher

Virginia Tech

Year dc:date.issued

2005

Author dc:creator

• Morford, Casey Justin

Chair dc:contributor.committeechair

• Patterson, Cameron D.

Committee members dc:contributor.committeemember

• Martin, Thomas L.
• Hsiao, Michael S.

• Field programmable gate arrays
• Partial Reconfiguration
• Virtex-II Pro
• Bitstream Manipulation
• Bitstream
• Xilinx
• Virtex-II
• Dynamic Module Server

Statement dc:rights

• In Copyright

Licence dc:rights.uri

• http://rightsstatements.org/vocab/InC/1.0/

Language dc:language.iso

en

Dc Identifier Other

etd-12162005-144728

OAI identifier oai:identifier

oai:vtechworks.lib.vt.edu:10919/36198