Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 20 of 3272 for “"Bitstream"”.
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Open-Source Bitstream Generation for FPGAs
Bitstream generation has traditionally been the single part of the FPGA design flow that has not been openly reproduced. This work enables bitstream generation for "limited" resources without reverse-engineering or violating End-User License Agreement terms. Two use cases in particular have …
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BitMaT - Bitstream Manipulation Tool for Xilinx FPGAs
… BitMaT, a tool that provides the low-level bitstream manipulation as a member tool of an alternative, automated, modular partial reconfiguration flow.
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Error Resilient Video Coding Using Bitstream Syntax And Iterative Microscopy Image Segmentation
… for compression, typically making compressed bitstreams vulnerable to errors. We propose several adaptive spatial-temporal error concealment approaches for subsampling-based multiple description video coding. These adaptive methods are based on motion and mode information extracted from the …
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Measurement of the Ratio of Charged and Neutral 𝐵 Mesons in Υ (4𝑆) Events via Partial Reconstruction of the Semileptonic Decays 𝛣̅⁰⟶𝐷<sup>∗</sup>⁺ℓ⁻<sub>𝜈̅ℓ</sub> and 𝛣̅⁻⟶𝐷<sup>∗</sup>⁰ℓ<sub>𝜈̅ℓ</sub>
… align=center src=https://vtechworks.lib.vt.edu/bitstream/handle/10919/28846/image006.gif> and <img width=119 height=29 align=center src=https://vtechworks.lib.vt.edu/bitstream/handle/10919/28846/image008.gif> are studied using data collected at the CLEO II detector at the Cornell Electron …
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Rateless and rateless unequal error protection codes for Gaussian channels
… bits are decoded at the same time and thus the bitstream cannot be prioritized. In addition, if only a finite number of retransmissions is allowed, the range of available rates that a rateless code can provide is limited. In contrast, a UEP code provides a prioritization of the bitstream, and an …
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A Standalone Wire Database for Routing and Tracing in Xilinx Virtex, Virtex-E, and Virtex-II FPGAs
… scheme is to modify or generate configuration bitstreams directly, resulting in more dynamic designs and shorter processing times. This thesis introduces a complete set of alternate wire databases for Xilinx Virtex, Virtex-E, and Virtex-II FPGAs, suitable for standalone use or as an addition to …
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Protocols specification and validation for the movement of Grades 2 and 3 Bitstream data through the Virtual Channel Link Control layer of the return link of the CCSDS Principal Network (CPN)
… protocols specification for the movement of bitstream data through space segment by applying a formal definition technique known as the Language of Temporal Ordering System (LOTOS). Successful generation of the LOTOS specification to detail sequence of events and their internal structures in …
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A Modular Flow for Rapid FPGA Design Implementation
… modules and associated meta-data to enable bitstream-level assembly of desired designs. In so doing, assembly would occur in a fraction of the time of traditional back-end tools. Modules could be bound, placed, and routed using custom bitstream assembly with the primary objective of rapid …
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Design and development of a vulnerability detection framework using artificial intelligence for embedded systems
… vulnerabilities in FPGA based systems, such as bitstream manipulation and HDL coding flaws. We introduce the BitVul-LLM model for detecting FPGA bitstream vulnerabilities, and SecureLLAMA, a transformer-based framework using the FPGAvul dataset to identify hardware security risks. These models …
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Error detection and error concealment for MPEG2 over communication networks
… the redundancies that the syntax of compressed bitstream provides. The performance of those two schemes were compared against a general error correcting scheme.
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A timeshared, runtime reconfigurable hardware co-processing architecture
… bitparse and bitrender, to demonstrate the bitstream relocation technique. Further, we present a functional microprocessor system coupled with a runtime reprogramable peripheral synthesized on a Xilinx Virtex-5 FPGA and discuss its performance implications.
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Selective lossless retention of critical thermal data within highly compressed thermal video sequences
… as an MPEG-1, MPEG-2 and MPEG4 compliant bitstream. This novel storage mechanism allows the error recovery codes to be spatially mapped to the ROl data, and hence the scheme can benefit from the motion compensation facilities provided within the MPEG compliant bitstream. Decoding of the …
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Error relilient video communications using high level M-QAM. Modelling and simulation of a comparative analysis of a dual-priority M-QAM transmission system for H.264/AVC video applications over band-limited and error-phone channels.
… and unequal error protection to make the video bitstream robust to channel errors. An implementation is described in which H.264 video is protected unequally by partitioning the compressed data into two layers of different visual importance. The partition scheme is based on a separation of the …
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Runtime Intellectual Property Protection on Programmable Platforms
… limited, and do not reach beyond whole-design bitstream encryption. This work presents an architecture and protocol for securing IP based designs in programmable platforms. The architecture is reprsented by the Secure Authentication Module (SAM), an enabler for next-generation …
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Timing-Aware Automatic Floorplanning of Partially Reconfigurable Designs for Accelerating FPGA Productivity
… is still rapid because the partial bitstream for each block is generated by independent concurrent invocations of the standard Xilinx tools.
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A Device-Level FPGA Simulator
… device. The only input required by VTsim is a bitstream, which can be generated from any tool suite. The simulator is part of the JHDLBits open-source project, and was designed for rapid response, low memory usage, and ease of interaction.
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Computing with Spintronics: Circuits and architectures
… SC, data is encoded in the form of pseudo-random bitstreams, such that the probability of a '1' in a bitstream corresponds to the numerical value that it represents. SC can enable compact, low-complexity logic implementations of various arithmetic functions. Spintastic establishes the synergy …
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Systematic hybrid analog/digital signal coding
… transformation, 2) quantization, and 3) lossless bitstream coding. The paradigm has been applied with great success to conventional source coding, and it applies equally well to systematic source coding. Focusing on the case involving a Gaussian source, Gaussian channel and mean-squared …
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An FPGA-based Run-time Reconfigurable 2-D Discrete Wavelet Transform Core
… tools that bypass the traditional synthesis and bitstream generation process for FPGAs become available. The JBits tool suite is an environment that provides support for RTR designs on Xilinx Virtex and 4K devices. This research provides a comprehensive design process description of a …
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Simulation of a binary phase shift keyed receiver with an IF correlator for position location
… the data demodulator. It correlates the incoming bitstream with a fixed reference bit sequence (synchronization header) to find the beginning of a data message. For position location applications this correlator is used to record the time of arrival of the signal at the receiver. These correlators …
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