Model Development, Synthesis and Validation Using the Modeler's Assistant

This thesis discusses 'Modeler's Assistant', an interactive graphics tool which aids in the rapid development of VHDL models. The tool provides modeling, test bench generation, simulation, synthesis and validation features. The 'Process Model graph' which has representations for the concurrent processes is used as the basis for Modeler's Assistant. Test generation environment is integrated into the tool. A range of test bench options are provided to the user. The tool interfaces to 'Synopsys' VHDL analyzer, graphics debugger and synthesis tools. Validation of the behavioral model versus the synthesized structural model is also discussed. A detailed programming manual with many examples is provided for the benefit of the user.

Name thesis:degree_name

Master of Science

Level thesis:degree_level

masters

Discipline thesis:degree_discipline

Electrical and Computer Engineering

Department dc:contributor.department

Electrical and Computer Engineering

Grantor dc:publisher

Virginia Tech

Year dc:date.issued

1999

Author dc:creator

• Narnur, Soumya

Chair dc:contributor.committeechair

• Armstrong, James R.

Committee members dc:contributor.committeemember

• Ha, Dong Sam
• Gray, Festus Gail

• Synthesis
• Validation
• VHDL Modeling

Statement dc:rights

• In Copyright

Licence dc:rights.uri

• http://rightsstatements.org/vocab/InC/1.0/

Dc Identifier Other

etd-081299-184716

OAI identifier oai:identifier

oai:vtechworks.lib.vt.edu:10919/34500