{"id":{"repo_id":"vt","oai_identifier":"oai:vtechworks.lib.vt.edu:10919/34500"},"canonical_url":"https://search.dev.ndltd.org/etd/vt/oai:vtechworks.lib.vt.edu:10919/34500","repository":{"repo_id":"vt","name":"Virginia Tech","base_url":"https://vtechworks.lib.vt.edu/oai/request"},"display":{"title":"Model Development, Synthesis and Validation Using the Modeler's Assistant","abstract":"This thesis discusses 'Modeler's Assistant', an interactive graphics tool which aids in the rapid development of VHDL models. The tool provides modeling, test bench generation, simulation, synthesis and validation features. The 'Process Model graph' which has representations for the concurrent processes is used as the basis for Modeler's Assistant. Test generation environment is integrated into the tool. A range of test bench options are provided to the user. The tool interfaces to 'Synopsys' VHDL analyzer, graphics debugger and synthesis tools. Validation of the behavioral model versus the synthesized structural model is also discussed. A detailed programming manual with many examples is provided for the benefit of the user.","abstract_html":"This thesis discusses 'Modeler's Assistant', an interactive graphics tool which aids in the rapid development of VHDL models. The tool provides modeling, test bench generation, simulation, synthesis and validation features. The 'Process Model graph' which has representations for the concurrent processes is used as the basis for Modeler's Assistant. Test generation environment is integrated into the tool. A range of test bench options are provided to the user. The tool interfaces to 'Synopsys' VHDL analyzer, graphics debugger and synthesis tools. Validation of the behavioral model versus the synthesized structural model is also discussed. A detailed programming manual with many examples is provided for the benefit of the user.","abstract_has_math":false,"creators":["Narnur, Soumya"],"institution":"Virginia Tech","degree_name":"Master of Science","degree_level":"masters","degree_discipline":"Electrical and Computer Engineering","degree_department":"Electrical and Computer Engineering","school":null,"contributors":[],"advisors":[],"committee_chairs":["Armstrong, James R."],"committee_members":["Ha, Dong Sam","Gray, Festus Gail"],"year":1999,"date_issued":"1999-08-06","date_published":"1999-08-06","updated_at":"2026-07-22T22:18:46Z","subjects":["Synthesis","Validation","VHDL Modeling"],"languages":[],"rights":["In Copyright"],"rights_urls":["http://rightsstatements.org/vocab/InC/1.0/"],"identifier_entries":[{"key":"dc:identifier.other","label":"Dc Identifier Other","values":["etd-081299-184716"],"render_values":[{"text":"etd-081299-184716","href":null,"code":true}]}]},"links":{"outbound_url":"http://hdl.handle.net/10919/34500","outbound_label":"Handle","outbound_source":"dc:identifier.uri"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor.committeechair","label":"Committee Chair","values":["Armstrong, James R."]},{"key":"dc:contributor.committeemember","label":"Committee Member","values":["Ha, Dong Sam","Gray, Festus Gail"]},{"key":"dc:contributor.department","label":"Department","values":["Electrical and Computer Engineering"]},{"key":"dc:creator","label":"Author","values":["Narnur, Soumya"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date.accessioned","label":"Dc Date Accessioned","values":["2014-03-14T20:43:21Z"]},{"key":"dc:date.available","label":"Dc Date Available","values":["2014-03-14T20:43:21Z","2000-08-14"]},{"key":"dc:date.issued","label":"Date","values":["1999-08-06"]},{"key":"dc:publisher","label":"Institution","values":["Virginia Tech"]},{"key":"dc:type","label":"Dc Type","values":["Thesis"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical and Computer Engineering"]},{"key":"thesis:degree_level","label":"Degree Level","values":["masters"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Master of Science"]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["Virginia Polytechnic Institute and State University"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Synthesis","Validation","VHDL Modeling"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:rights","label":"Dc Rights","values":["In Copyright"]},{"key":"dc:rights.uri","label":"Rights URI","values":["http://rightsstatements.org/vocab/InC/1.0/"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier.other","label":"Dc Identifier Other","values":["etd-081299-184716"]},{"key":"dc:identifier.uri","label":"Identifier URI","values":["http://hdl.handle.net/10919/34500"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description.abstract","label":"Abstract","values":["This thesis discusses 'Modeler's Assistant', an interactive graphics tool which aids in the rapid development of VHDL models. The tool provides modeling, test bench generation, simulation, synthesis and validation features. The 'Process Model graph' which has representations for the concurrent processes is used as the basis for Modeler's Assistant. Test generation environment is integrated into the tool. A range of test bench options are provided to the user. The tool interfaces to 'Synopsys' VHDL analyzer, graphics debugger and synthesis tools. Validation of the behavioral model versus the synthesized structural model is also discussed. A detailed programming manual with many examples is provided for the benefit of the user."]},{"key":"dc:description.degree","label":"Dc Description Degree","values":["Master of Science"]},{"key":"dc:title","label":"Title","values":["Model Development, Synthesis and Validation Using the Modeler's Assistant"]}]}],"canonical_facts":{"dc:contributor.committeechair":["Armstrong, James R."],"dc:contributor.committeemember":["Ha, Dong Sam","Gray, Festus Gail"],"dc:contributor.department":["Electrical and Computer Engineering"],"dc:creator":["Narnur, Soumya"],"dc:date.accessioned":["2014-03-14T20:43:21Z"],"dc:date.available":["2014-03-14T20:43:21Z","2000-08-14"],"dc:date.issued":["1999-08-06"],"dc:description.abstract":["This thesis discusses 'Modeler's Assistant', an interactive graphics tool which aids in the rapid development of VHDL models. The tool provides modeling, test bench generation, simulation, synthesis and validation features. The 'Process Model graph' which has representations for the concurrent processes is used as the basis for Modeler's Assistant. Test generation environment is integrated into the tool. A range of test bench options are provided to the user. The tool interfaces to 'Synopsys' VHDL analyzer, graphics debugger and synthesis tools. Validation of the behavioral model versus the synthesized structural model is also discussed. A detailed programming manual with many examples is provided for the benefit of the user."],"dc:description.degree":["Master of Science"],"dc:identifier.other":["etd-081299-184716"],"dc:identifier.uri":["http://hdl.handle.net/10919/34500"],"dc:publisher":["Virginia Tech"],"dc:rights":["In Copyright"],"dc:rights.uri":["http://rightsstatements.org/vocab/InC/1.0/"],"dc:subject":["Synthesis","Validation","VHDL Modeling"],"dc:title":["Model Development, Synthesis and Validation Using the Modeler's Assistant"],"dc:type":["Thesis"],"thesis:degree_discipline":["Electrical and Computer Engineering"],"thesis:degree_level":["masters"],"thesis:degree_name":["Master of Science"],"thesis:institution_name":["Virginia Polytechnic Institute and State University"]},"updated_at":"2026-07-22T22:18:46Z"}