A Design Assembly Technique for FPGA Back-End Acceleration

Long wait times constitute a bottleneck limiting the number of compilation runs performed in a day, thus risking to restrict Field-Programmable Gate Array (FPGA) adaptation in modern computing platforms. This work presents an FPGA development paradigm that exploits logic variance and hierarchy as a means to increase FPGA productivity. The practical tasks of logic partitioning, placement and routing are examined and a resulting assembly framework, Quick Flow (qFlow), is implemented. Experiments show up to 10x speed-ups using the proposed paradigm compared to vendor tool flows.

Name thesis:degree_name

Ph. D.

Level thesis:degree_level

doctoral

Discipline thesis:degree_discipline

Electrical and Computer Engineering

Department dc:contributor.department

Electrical and Computer Engineering

Grantor dc:publisher

Virginia Tech

Year dc:date.issued

2012

Author dc:creator

• Frangieh, Tannous

Chair dc:contributor.committeechair

• Athanas, Peter M.

Committee members dc:contributor.committeemember

• Schaumont, Patrick R.
• Nelson, Brent E.
• Dietrich, Carl B.
• Feng, Wu-chun

• Configurable Computing
• FPGA Productivity
• Design Assembly Flow
• Electronic Design Automation
• Design Reuse

Statement dc:rights

• In Copyright

Licence dc:rights.uri

• http://rightsstatements.org/vocab/InC/1.0/

Dc Identifier Other

etd-10082012-021855

OAI identifier oai:identifier

oai:vtechworks.lib.vt.edu:10919/29225