{"id":{"repo_id":"vt","oai_identifier":"oai:vtechworks.lib.vt.edu:10919/29225"},"canonical_url":"https://search.dev.ndltd.org/etd/vt/oai:vtechworks.lib.vt.edu:10919/29225","repository":{"repo_id":"vt","name":"Virginia Tech","base_url":"https://vtechworks.lib.vt.edu/oai/request"},"display":{"title":"A Design Assembly Technique for FPGA Back-End Acceleration","abstract":"Long wait times constitute a bottleneck limiting the number of compilation runs performed in a day, thus risking to restrict Field-Programmable Gate Array (FPGA) adaptation in modern computing platforms. This work presents an FPGA development paradigm that exploits logic variance and hierarchy as a means to increase FPGA productivity. The practical tasks of logic partitioning, placement and routing are examined and a resulting assembly framework, Quick Flow (qFlow), is implemented. Experiments show up to 10x speed-ups using the proposed paradigm compared to vendor tool flows.","abstract_html":"Long wait times constitute a bottleneck limiting the number of compilation runs performed in a day, thus risking to restrict Field-Programmable Gate Array (FPGA) adaptation in modern computing platforms. This work presents an FPGA development paradigm that exploits logic variance and hierarchy as a means to increase FPGA productivity. The practical tasks of logic partitioning, placement and routing are examined and a resulting assembly framework, Quick Flow (qFlow), is implemented. Experiments show up to 10x speed-ups using the proposed paradigm compared to vendor tool flows.","abstract_has_math":false,"creators":["Frangieh, Tannous"],"institution":"Virginia Tech","degree_name":"Ph. D.","degree_level":"doctoral","degree_discipline":"Electrical and Computer Engineering","degree_department":"Electrical and Computer Engineering","school":null,"contributors":[],"advisors":[],"committee_chairs":["Athanas, Peter M."],"committee_members":["Schaumont, Patrick R.","Nelson, Brent E.","Dietrich, Carl B.","Feng, Wu-chun"],"year":2012,"date_issued":"2012-09-28","date_published":"2012-09-28","updated_at":"2026-07-22T22:18:53Z","subjects":["Configurable Computing","FPGA Productivity","Design Assembly Flow","Electronic Design Automation","Design Reuse"],"languages":[],"rights":["In Copyright"],"rights_urls":["http://rightsstatements.org/vocab/InC/1.0/"],"identifier_entries":[{"key":"dc:identifier.other","label":"Dc Identifier Other","values":["etd-10082012-021855"],"render_values":[{"text":"etd-10082012-021855","href":null,"code":true}]}]},"links":{"outbound_url":"http://hdl.handle.net/10919/29225","outbound_label":"Handle","outbound_source":"dc:identifier.uri"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor.committeechair","label":"Committee Chair","values":["Athanas, Peter M."]},{"key":"dc:contributor.committeemember","label":"Committee Member","values":["Schaumont, Patrick R.","Nelson, Brent E.","Dietrich, Carl B.","Feng, Wu-chun"]},{"key":"dc:contributor.department","label":"Department","values":["Electrical and Computer Engineering"]},{"key":"dc:creator","label":"Author","values":["Frangieh, Tannous"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date.accessioned","label":"Dc Date Accessioned","values":["2014-03-14T20:17:11Z"]},{"key":"dc:date.available","label":"Dc Date Available","values":["2014-03-14T20:17:11Z","2012-10-19"]},{"key":"dc:date.issued","label":"Date","values":["2012-09-28"]},{"key":"dc:publisher","label":"Institution","values":["Virginia Tech"]},{"key":"dc:type","label":"Dc Type","values":["Dissertation"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical and Computer Engineering"]},{"key":"thesis:degree_level","label":"Degree Level","values":["doctoral"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Ph. D."]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["Virginia Polytechnic Institute and State University"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Configurable Computing","FPGA Productivity","Design Assembly Flow","Electronic Design Automation","Design Reuse"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:rights","label":"Dc Rights","values":["In Copyright"]},{"key":"dc:rights.uri","label":"Rights URI","values":["http://rightsstatements.org/vocab/InC/1.0/"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier.other","label":"Dc Identifier Other","values":["etd-10082012-021855"]},{"key":"dc:identifier.uri","label":"Identifier URI","values":["http://hdl.handle.net/10919/29225"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description.abstract","label":"Abstract","values":["Long wait times constitute a bottleneck limiting the number of compilation runs performed in a day, thus risking to restrict Field-Programmable Gate Array (FPGA) adaptation in modern computing platforms. This work presents an FPGA development paradigm that exploits logic variance and hierarchy as a means to increase FPGA productivity. The practical tasks of logic partitioning, placement and routing are examined and a resulting assembly framework, Quick Flow (qFlow), is implemented. Experiments show up to 10x speed-ups using the proposed paradigm compared to vendor tool flows."]},{"key":"dc:description.degree","label":"Dc Description Degree","values":["Ph. D."]},{"key":"dc:title","label":"Title","values":["A Design Assembly Technique for FPGA Back-End Acceleration"]}]}],"canonical_facts":{"dc:contributor.committeechair":["Athanas, Peter M."],"dc:contributor.committeemember":["Schaumont, Patrick R.","Nelson, Brent E.","Dietrich, Carl B.","Feng, Wu-chun"],"dc:contributor.department":["Electrical and Computer Engineering"],"dc:creator":["Frangieh, Tannous"],"dc:date.accessioned":["2014-03-14T20:17:11Z"],"dc:date.available":["2014-03-14T20:17:11Z","2012-10-19"],"dc:date.issued":["2012-09-28"],"dc:description.abstract":["Long wait times constitute a bottleneck limiting the number of compilation runs performed in a day, thus risking to restrict Field-Programmable Gate Array (FPGA) adaptation in modern computing platforms. This work presents an FPGA development paradigm that exploits logic variance and hierarchy as a means to increase FPGA productivity. The practical tasks of logic partitioning, placement and routing are examined and a resulting assembly framework, Quick Flow (qFlow), is implemented. Experiments show up to 10x speed-ups using the proposed paradigm compared to vendor tool flows."],"dc:description.degree":["Ph. D."],"dc:identifier.other":["etd-10082012-021855"],"dc:identifier.uri":["http://hdl.handle.net/10919/29225"],"dc:publisher":["Virginia Tech"],"dc:rights":["In Copyright"],"dc:rights.uri":["http://rightsstatements.org/vocab/InC/1.0/"],"dc:subject":["Configurable Computing","FPGA Productivity","Design Assembly Flow","Electronic Design Automation","Design Reuse"],"dc:title":["A Design Assembly Technique for FPGA Back-End Acceleration"],"dc:type":["Dissertation"],"thesis:degree_discipline":["Electrical and Computer Engineering"],"thesis:degree_level":["doctoral"],"thesis:degree_name":["Ph. D."],"thesis:institution_name":["Virginia Polytechnic Institute and State University"]},"updated_at":"2026-07-22T22:18:53Z"}