GaN Device Characterization, Converter Optimization and Development for Enhanced Aviation Systems

GaN device is one of the most promising candidates in high-efficiency and high-density power conversion applications. Due to the low ON-Resistance GaN devices are widely adopted in various soft-switching converters. Based on superior Baliga's Figure of Merit, GaN devices also have advantages over SiC and Si devices in hard switching conditions. However, the existence of dynamic R_DS(on) weakens the advantage on the low conduction loss. The small footprint limits the heat dissipation ability hence the maximum switching frequency.Further improvement of power density may have constraints from passive components, which requires systematic optimization of GaN-based high-density converters.\\ By designing a multi-purpose testing platform, the dynamic R_DS(on) of one GaN device is characterized under both DPT and soft-switching continuous tests, with different junction temperatures . Normalized R_DS(on) is quantified and compared. The data can then be used to estimate extra loss from the dynamic R_DS(on) under realistic power converter operating conditions.\\ The advantage of lower R_DS(on) is especially prominent on low-Voltage rated GaN devices, which makes multi-level topology more preferable for GaN-based converters. A three-level Totem pole PFC converter for aircraft in-seat power supply is designed and optimized. The three-level topology enables the selection of the 200 V GaN device, leading to smaller conduction loss and a 98.4\% peak efficiency. With the help of the PR compensator and input voltage feedforward, the phase-leading problem caused by the digital delay is greatly reduced and proven in 800Hz line frequency. The THD can meet the standard by doubling the sampling frequency and improving sensing. The EMI performance also meets the requirement with a one-stage filter at ac side and a common-mode inductor on the DC bus.\\ For inverter design of unmanned aerial vehicle applications where there's a lower voltage DC-link, two-level gains advantage over three level after systematic optimization and evaluation on the weight and loss. Paralleling up to four GaN devices effectively balanced the switching and conduction loss. By designing the power loop inductance to 0.11 nH, 100V GaN devices were safely operated under a 70 V DC bus with only a maximum 9.8 V overshoot. To prevent the inverter from short-circuit faults, the short-circuit protection based on the measurement of the voltage on the power loop inductor with a low-pass filter is successfully applied with only 115 ns protection time. The designed prototype shows expected thermal performance under rated 3.3 kVA power and survives a two-second 5.1 kVA transient power.

Name thesis:degree_name

Doctor of Philosophy

Level thesis:degree_level

doctoral

Discipline thesis:degree_discipline

Electrical Engineering

Department dc:contributor.department

Electrical Engineering

Grantor dc:publisher

Virginia Tech

Year dc:date.issued

2026

Author dc:creator

• Zhao, Tianyu

Chair dc:contributor.committeechair

• Burgos, Rolando

Committee members dc:contributor.committeemember

• Lu, Guo Quan
• Zhang, Yuhao
• Mehrizi-Sani, Ali
• Dong, Dong

• GaN
• Device Characterization
• Optimization
• AC-DC
• DC-AC

Statement dc:rights

• In Copyright

Licence dc:rights.uri

• http://rightsstatements.org/vocab/InC/1.0/

Language dc:language.iso

en

Dc Identifier Other

vt_gsexam:45563

OAI identifier oai:identifier

oai:vtechworks.lib.vt.edu:10919/141229