Efficient RSA Cryptosystems Immune against the Hardware Fault Attack and the FPGA Implementations

In this thesis, new algorithms and structures with immunity against the hardware fault attack for CRT-based two-prime and multi-prime RSA cryptosystems are proposed, investigated, and compared to the previous work. The VLSI implementations of these cryptosystems are carried out in the thesis project and the results are presented, which demonstrate the advantages of the proposed algorithms. It is found that the proposed new algorithms provide more efficient operation speed and use fewer hardware resources than previous work. The standard CRT-based two-prime RSA cryptosystem is vulnerable to the hardware fault attack, and thus a novel two-prime RSA that is immune against such attack is proposed in this thesis. The properties in terms of the factorization complexity and the operation speed of the proposed two-prime RSA are compared with the previous work, the CRT-2 protocol proposed by Yen et al. It is proven that the proposed new two-prime RSA cryptosystem provides higher operation speed than CRT-2 protocol, and bears similar factorization complexity as CRT-2 protocol. Furthermore, the factorization complexity analysis of standard CRT-based multi-prime RSA using the hardware fault attack method is carried out. It is found out that the CRT-based multi-prime RSA with more prime factors bears more difficulty for the hardware fault attacker. Then, efficient multi-prime RSA cryptosystems immune against the hardware fault attack is proposed. The proposed multi-prime RSA is proven to bear similar factorization complexity to the hardware fault attack and provide higher operation speed than extended CRT-2 protocol. The two-prime and three-prime RSA using the standard CRT-based method, the CRT-2 protocol, as well as the proposed methods are implemented using FPGA technology. The implementation results with respect to the resources usage and data throughput rate of different systems are compared. The implementation results show that the proposed CRT-based RSA cryptosystems use fewer resources, and provide higher data throughput rate than those based on CRT-2 protocol.

Name thesis:degree_name

Master of Engineering Science

Discipline thesis:degree_discipline

Electrical and Computer Engineering Science

Grantor dc:publisher

The University of Western Ontario

Year dc:date.issued

2004

Author dc:creator

• Yang, Yonghong

• RSA cryptography
• Chinese Remainder Theorem
• hardware fault attack
• VLSI
• FPGA implementation

Language dc:language.iso

en

Handle dc:identifier.uri

https://hdl.handle.net/20.500.14721/38995

OAI identifier oai:identifier

oai:uwo.scholaris.ca:20.500.14721/38995