Process Variation Aware DRAM (Dynamic Random Access Memory) Design Using Block-Based Adaptive Body Biasing Algorithm

Desai, Satyajit

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Process Variation Aware DRAM (Dynamic Random Access Memory) Design Using Block-Based Adaptive Body Biasing Algorithm

dc:creator Desai, Satyajit

thesis:degree_name Master of Science (MS)

Degree

thesis:*

Name thesis:degree_name: Master of Science (MS)
Level thesis:degree_level: Thesis
Grantor dc:publisher: Hosted by Utah State University Libraries

Author and committee

dc:creator, dc:contributor.*

Author dc:creator: Desai, Satyajit
Contributors dc:contributor: Sanghamitra Roy
Koushik Chakraborty
Reyhan Bhaktur

Subjects

dc:subject × 3

Identifiers

dc:identifier.*

Repository record dc:identifier: https://digitalcommons.usu.edu/etd/1419
OAI identifier oai:identifier: oai:digitalcommons.usu.edu:etd-2388

Chain of custody

source

Harvested from: Utah State University
Base URL: digitalcommons.usu.edu/do/oai/
Last updated: 2026-07-27
Source record: OAI-PMH GetRecord

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citation

Desai, Satyajit. Process Variation Aware DRAM (Dynamic Random Access Memory) Design Using Block-Based Adaptive Body Biasing Algorithm. Thesis thesis, Hosted by Utah State University Libraries, https://digitalcommons.usu.edu/etd/1419

Process Variation Aware DRAM (Dynamic Random Access Memory) Design Using Block-Based Adaptive Body Biasing Algorithm

Degree

Author and committee

Subjects

Identifiers

Chain of custody

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