High Performance Architecture using Speculative Threads and Dynamic Memory Management Hardware

With the advances in very large scale integration (VLSI) technology, hundreds of billions of transistors can be packed into a single chip. With the increased hardware budget, how to take advantage of available hardware resources becomes an important research area. Some researchers have shifted from control flow Von-Neumann architecture back to dataflow architecture again in order to explore scalable architectures leading to multi-core systems with several hundreds of processing elements. In this dissertation, I address how the performance of modern processing systems can be improved, while attempting to reduce hardware complexity and energy consumptions. My research described here tackles both central processing unit (CPU) performance and memory subsystem performance. More specifically I will describe my research related to the design of an innovative decoupled multithreaded architecture that can be used in multi-core processor implementations. I also address how memory management functions can be off-loaded from processing pipelines to further improve system performance and eliminate cache pollution caused by runtime management functions.

Grantor dc:publisher

University of North Texas

Year dc:date

2007

Author dc:creator

• Li, Wentong

Contributors dc:contributor

• Kavi, Krishna M.
• Sweany, Philip H.
• Brazile, Robert
• Mohanty, Saraju P.

• memory management
• speculation
• data flow architecture
• decoupled architecture
• Computer architecture.
• Memory management (Computer science)

Statement dc:rights

• Public
• Copyright
• Li, Wentong
• Copyright is held by the author, unless otherwise noted. All rights reserved.

Language dc:language

English

Identifier

oclc: 228427467
https://digital.library.unt.edu/ark:/67531/metadc5150/
ark: ark:/67531/metadc5150

OAI identifier oai:identifier

info:ark/67531/metadc5150