Characterizing within-die and die-to-die delay variations introduced By process variations and SOI history effect

Variations in delay caused by within-die and die-to-die process variations and SOI history effect increase timing margins and reduce performance. In order to develop mitigation techniques to reduce the detrimental effects of delay variations, particularly those that occur within-die, new methods of measuring delay variations within actual products are needed. The data provided by such techniques can also be used for validating models, i.e., can assist with model-to-hardware correlation. In this research work, a method is proposed for a flush delay technique to measure both regional delay variations and SOI history effect. The method is then validated using a test structure fabricated in a 65 nm SOI process.

Name thesis:degree_name

Computer Engineering

Level thesis:degree_level

Thesis

Discipline thesis:degree_discipline

Electrical and Computer Engineering

Year

2011

Author dc:creator

• Aarestad, James

Contributors dc:contributor

• Plusquellic, Jim
• Zarkesh-Ha, Payman
• Pattichis, Marios

• Delay faults (Semiconductors)
• Silicon-on-insulator technology.

Language dc:language

English

Repository record dc:identifier

https://digitalrepository.unm.edu/ece_etds/1

OAI identifier oai:identifier

oai:digitalrepository.unm.edu:ece_etds-1000