{"id":{"repo_id":"unm","oai_identifier":"oai:digitalrepository.unm.edu:ece_etds-1000"},"canonical_url":"https://search.dev.ndltd.org/etd/unm/oai:digitalrepository.unm.edu:ece_etds-1000","repository":{"repo_id":"unm","name":"University of New Mexico","base_url":"https://digitalrepository.unm.edu/do/oai/"},"display":{"title":"Characterizing within-die and die-to-die delay variations introduced By process variations and SOI history effect","abstract":"Variations in delay caused by within-die and die-to-die process variations and SOI history effect increase timing margins and reduce performance. In order to develop mitigation techniques to reduce the detrimental effects of delay variations, particularly those that occur within-die, new methods of measuring delay variations within actual products are needed. The data provided by such techniques can also be used for validating models, i.e., can assist with model-to-hardware correlation. In this research work, a method is proposed for a flush delay technique to measure both regional delay variations and SOI history effect. The method is then validated using a test structure fabricated in a 65 nm SOI process.","abstract_html":"Variations in delay caused by within-die and die-to-die process variations and SOI history effect increase timing margins and reduce performance. In order to develop mitigation techniques to reduce the detrimental effects of delay variations, particularly those that occur within-die, new methods of measuring delay variations within actual products are needed. The data provided by such techniques can also be used for validating models, i.e., can assist with model-to-hardware correlation. In this research work, a method is proposed for a flush delay technique to measure both regional delay variations and SOI history effect. The method is then validated using a test structure fabricated in a 65 nm SOI process.","abstract_has_math":false,"creators":["Aarestad, James"],"institution":null,"degree_name":"Computer Engineering","degree_level":"Thesis","degree_discipline":"Electrical and Computer Engineering","degree_department":null,"school":null,"contributors":["Plusquellic, Jim","Zarkesh-Ha, Payman","Pattichis, Marios"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2011,"date_issued":"2011-07-02T07:00:00Z","date_published":"2011-07-02T07:00:00Z","updated_at":"2026-07-24T05:27:10Z","subjects":["Delay faults (Semiconductors)","Silicon-on-insulator technology."],"languages":["English"],"rights":[],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"https://digitalrepository.unm.edu/ece_etds/1","outbound_label":"Repository record","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Plusquellic, Jim","Zarkesh-Ha, Payman","Pattichis, Marios"]},{"key":"dc:creator","label":"Author","values":["Aarestad, James"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical and Computer Engineering"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Thesis","Masters"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Computer Engineering"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Delay faults (Semiconductors)","Silicon-on-insulator technology."]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["English"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["https://digitalrepository.unm.edu/ece_etds/1"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description.abstract","label":"Abstract","values":["Variations in delay caused by within-die and die-to-die process variations and SOI history effect increase timing margins and reduce performance. In order to develop mitigation techniques to reduce the detrimental effects of delay variations, particularly those that occur within-die, new methods of measuring delay variations within actual products are needed. The data provided by such techniques can also be used for validating models, i.e., can assist with model-to-hardware correlation. In this research work, a method is proposed for a flush delay technique to measure both regional delay variations and SOI history effect. The method is then validated using a test structure fabricated in a 65 nm SOI process."]},{"key":"dc:title","label":"Title","values":["Characterizing within-die and die-to-die delay variations introduced By process variations and SOI history effect"]}]}],"canonical_facts":{"dc:contributor":["Plusquellic, Jim","Zarkesh-Ha, Payman","Pattichis, Marios"],"dc:creator":["Aarestad, James"],"dc:description.abstract":["Variations in delay caused by within-die and die-to-die process variations and SOI history effect increase timing margins and reduce performance. In order to develop mitigation techniques to reduce the detrimental effects of delay variations, particularly those that occur within-die, new methods of measuring delay variations within actual products are needed. The data provided by such techniques can also be used for validating models, i.e., can assist with model-to-hardware correlation. In this research work, a method is proposed for a flush delay technique to measure both regional delay variations and SOI history effect. The method is then validated using a test structure fabricated in a 65 nm SOI process."],"dc:identifier":["https://digitalrepository.unm.edu/ece_etds/1"],"dc:language":["English"],"dc:subject":["Delay faults (Semiconductors)","Silicon-on-insulator technology."],"dc:title":["Characterizing within-die and die-to-die delay variations introduced By process variations and SOI history effect"],"thesis:degree_discipline":["Electrical and Computer Engineering"],"thesis:degree_level":["Thesis","Masters"],"thesis:degree_name":["Computer Engineering"]},"updated_at":"2026-07-24T05:27:10Z"}