Multiple voltage scheme with frequency variation for power minimization of pipelined circuits at high-level synthesis

High-Level Synthesis (HLS) is defined as a translation process from a behavioral description into structural description. The high-level synthesis process consists of three interdependent phases: scheduling, allocation and binDing The order of the three phases varies depending on the design flow. There are three important quality measures used to support design decision, namely size, performance and power consumption. Recently, with the increase in portability, the power consumption has become a very dominant factor in the design of circuits. The aim of low-power high-level synthesis is to schedule operations to minimize switching activity and select low power modules while satisfying timing constraints. This thesis presents a heuristic that helps minimize power consumption by operating the functional units at multiple voltages and varied clock frequencies. The algorithm presented here deals with pipelined operations where multiple instance of the same operation are carried out. The algorithm was implemented using C++, on LINUX platform.

Name thesis:degree_name

Master of Engineering (ME)

Level thesis:degree_level

Thesis

Discipline thesis:degree_discipline

Electrical and Computer Engineering

Grantor dc:publisher

University of Nevada, Las Vegas

Year

2003

Author dc:creator

• Radhakrishnan, Bharath

Contributors dc:contributor

• Muthukumar Venkatesan

Statement dc:rights

• IN COPYRIGHT. For more information about this rights statement, please visit http://rightsstatements.org/vocab/InC/1.0/

Language dc:language

English

Identifier

https://oasis.library.unlv.edu/rtds/1560

OAI identifier oai:identifier

oai:oasis.library.unlv.edu:rtds-2559