Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 20 of 31 for “"High-Level Synthesis (HLS)"”.
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Open-source high-level synthesis of tensorflow dataflow graphs using LegUp
… into FPGA accelerators using the open-source high-level synthesis (HLS) tool LegUp. The Tensorflow computation graph is represented translated from an intermediate representation in Tensorflow's Accelerated Linear Algebra (XLA) compiler called High Level Optimizer (HLO). This is translated …
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Efficient Gaussian Random Number Generators in HLS4ML
… combines combinational logic and CLT to achieve high tail accuracy with reduced hardware costs. This thesis discusses the Multihat method implemented using High-Level Synthesis (HLS), optimized for scalability and integrated into HLS4ML as a custom layer for FPGA deployment. Results show the …
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Enhancing FPGA Synthesis for Space Applications: Performance Evaluation of ScaleHLS in the ADAPT Project
… thesis investigates the application of ScaleHLS, a high-level synthesis (HLS) tool, to enhance Field-Programmable Gate Array (FPGA) synthesis for space applications, with a focus on the Antarctic Demonstrator Advanced Particle-astrophysics Telescope (ADAPT) project. The study explores how …
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Trustworthy system development through high-level synthesis
Major processor manufacturers have embraced the high-level synthesis (HLS) design philosophy. HLS offers the potential to explore the design space of electronic circuits and systems more efficiently than traditional methods. In this thesis, we investigate the ap-plication of HLS to …
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High Level Synthesis and Evaluation of the Secure Hash Standard for FPGAs
… which are tedious and time consuming. High Level Synthesis (HLS) enables designers to synthesize optimized FPGA hardware from algorithm specifications in programming languages such as C/C++. This substantially reduces the design cost and time. In this thesis, the Altera SDK for OpenCL …
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Multiple voltage scheme with frequency variation for power minimization of pipelined circuits at high-level synthesis
High-Level Synthesis (HLS) is defined as a translation process from a behavioral description into structural description. The high-level synthesis process consists of three interdependent phases: scheduling, allocation and binDing The order of the three phases varies depending on the design flow. …
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VAST-LP: clock gating in high-level synthesis
High-level synthesis (HLS) promises high-quality hardware with minimal develop- ment e ort. In this thesis, we evaluate the current state-of-the-art HLS engine VAST and propose a method to generate clock-gating-friendly RTL code for downstream logic synthesis tools. We use one-hot-key encoding …
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Hardware Accelerator Generation Framework for Cryptographic Primitives
… resource and latency-constrained environments. High-Level Synthesis (HLS) generates hardware from high-level implementations in languages like C, enabling the rapid prototyping and evaluation of designs, leading to its prominent use in developing dedicated hardware accelerators. However, …
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Efficient methods for mapping neural machine translator on FPGAs
… exploit the capability of FPGAs for delivering highly efficient implementations for real-life NMT applications. In our work, we map the inference of a large-scale NMT model with total computation of 172 GFLOP to a highly optimized high-level synthesis (HLS) IP and integrate the IP into Xilinx …
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Resource and data optimization for hardware implementation of deep neural networks targeting FPGA-based edge devices
… neural networks (CNNs), we adopt the high level synthesis (HLS) design methodology and explore various optimization and synthesis techniques to optimize design on an FPGA. Our motivation is to target embedded devices that operate as edge devices. Recently, as machine learning …
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High-level synthesis and its application in the design of Reed-Solomon decoders
… about by recent advanced in VLSI technology. High-level Synthesis (HLS) is a major part of VLSI design process. Its techniques can be used to yield an optimal result in the design. Yet, major applications of HLS methods are on digital filters or DSP circuits. Arithmetic in these circuits are …
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Generic FPGA Preprocessing for Astrophysics Instruments in HLS
<p>FPGAs are widely deployed on high-energy astroparticle physics instruments to preprocess large volumes of streaming data from various sensors. Increasingly, these deployments are finding their way to space-borne instruments, where constraints on size, weight, and power (SWaP) require careful …
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Characterization of Sparsity-aware Optimization Paths for Graph Traversal on FPGA
… on hardware description languages (HDLs) and high-level synthesis (HLS), address the memory-access bottleneck of BFS by using techniques such as data alignment and compute-unit replication on FPGAs. The efficacy of such optimizations depends on factors such as the sparsity of target graph …
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Classification of road side material using convolutional neural network and a proposed implementation of the network through Zedboard Zynq 7000 FPGA
… test images. In the second part of the research, High Level Synthesis (HLS) hardware model of the network with 16 Neuron inputs is created for the Zynq 7000 FPGA. The resulting circuit has 34% average FPGA utilization and 2.47 Watt power consumption. Recommendations to improve the classi cation …
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High-level automation of custom hardware design for high-performance computing
… efficient generation of custom processors from high-level language descriptions. Our work exploits compiler-based optimizations and transformations in tandem with high-level synthesis (HLS) to build high-performance custom processors. The goal is to offer a common multiplatform high-abstraction …
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Dafny-HLS: verified and optimized high-level synthesis via MLIR with LLM-assisted bug repair
High-Level Synthesis (HLS) improves hardware design productivity by generating Register-Transfer Level (RTL) from high-level language descriptions (e.g., C/C++). While recent MLIR-based HLS frameworks enable multi-level optimization and automated design space exploration, they are based on the …
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Chimera: An efficient design space exploration tool for FPGA high-level synthesis
… and power efficiency. However, with the high flexibility comes the difficulty in design and optimizations. Conventionally, the FPGA designs are written in low-level hardware descriptive languages, which means creating larger designs with complex behavior is extremely difficult. Therefore, …
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From Software Threads to Parallel Hardware with LegUp High-level Synthesis
High-level synthesis (HLS) can automatically synthesize software to hardware. With the design specification in software, HLS can reduce the lengthy design cycles of hardware, and make the performance and energy-efficiency benefits of hardware accessible to those without hardware skills. Since the …
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Using Workload Characterization to Guide High Performance Graph Processing
… of graph solvers. The introduction of High Level Synthesis (HLS) tools allowed FPGAs to be accessible to the masses but they are yet to be performant and efficient, especially in the case of irregular graph applications. Therefore, this dissertation proposes automated frameworks to help …
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High-level synthesis of triple modular redundant FPGA circuits with energy efficient error recovery mechanisms
… space due to their low cost, reconfigurability, high logic capacity and rich I/O interfaces. However, their configuration memory (CM) is vulnerable to ionising radiation which raises the need for effective fault-tolerant design techniques. This thesis provides the following contributions to …
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