Partitioning of large HDL ASIC designs into multiple FPGA devices for prototyping and verification

The ASIC (Application specific Integrated Circuit) designs grow continuously bigger and bigger. This causes dramatic increase in the simulation run time. It is very hard to simulate these designs because the simulation time has risen from hours to days and weeks. Hardware Embedded Simulation (HES) is a technology that facilitates incremental design verification of ASICs. The FPGAs (Field Programmable Gate Arrays) can play an important role in ASIC design cycle. But it is not possible to fit an entire ASIC design into a single FPGA device. This problem can be solved by partitioning the given design into multiple small size designs (modules) and fitting those modules into multiple FPGAs. The purpose of my thesis is to take a large RTL (Register Transfer Level) design of an ASIC into consideration, write and test the software ("C" code) practically to synthesize each top level module and analyze the size of each module in terms of number of CLBs (Configurable Logic Blocks), I/Os, flip-flops, latches and apply the algorithm to partition it automatically into minimum number of FPGAs.

Name thesis:degree_name

Master of Science (MS)

Level thesis:degree_level

Thesis

Discipline thesis:degree_discipline

Electrical and Computer Engineering

Grantor dc:publisher

University of Nevada, Las Vegas

Year

2000

Author dc:creator

• Dhavlikar, Nilesh V

Contributors dc:contributor

• Henry Selvaraj

Statement dc:rights

• IN COPYRIGHT. For more information about this rights statement, please visit http://rightsstatements.org/vocab/InC/1.0/

Language dc:language

English

Identifier

https://oasis.library.unlv.edu/rtds/1240

OAI identifier oai:identifier

oai:oasis.library.unlv.edu:rtds-2239