{"id":{"repo_id":"unlv","oai_identifier":"oai:oasis.library.unlv.edu:rtds-2239"},"canonical_url":"https://search.dev.ndltd.org/etd/unlv/oai:oasis.library.unlv.edu:rtds-2239","repository":{"repo_id":"unlv","name":"University of Nevada - Las Vegas","base_url":"https://oasis.library.unlv.edu/do/oai/"},"display":{"title":"Partitioning of large HDL ASIC designs into multiple FPGA devices for prototyping and verification","abstract":"The ASIC (Application specific Integrated Circuit) designs grow continuously bigger and bigger. This causes dramatic increase in the simulation run time. It is very hard to simulate these designs because the simulation time has risen from hours to days and weeks. Hardware Embedded Simulation (HES) is a technology that facilitates incremental design verification of ASICs. The FPGAs (Field Programmable Gate Arrays) can play an important role in ASIC design cycle. But it is not possible to fit an entire ASIC design into a single FPGA device. This problem can be solved by partitioning the given design into multiple small size designs (modules) and fitting those modules into multiple FPGAs. The purpose of my thesis is to take a large RTL (Register Transfer Level) design of an ASIC into consideration, write and test the software (\"C\" code) practically to synthesize each top level module and analyze the size of each module in terms of number of CLBs (Configurable Logic Blocks), I/Os, flip-flops, latches and apply the algorithm to partition it automatically into minimum number of FPGAs.","abstract_html":"The ASIC (Application specific Integrated Circuit) designs grow continuously bigger and bigger. This causes dramatic increase in the simulation run time. It is very hard to simulate these designs because the simulation time has risen from hours to days and weeks. Hardware Embedded Simulation (HES) is a technology that facilitates incremental design verification of ASICs. The FPGAs (Field Programmable Gate Arrays) can play an important role in ASIC design cycle. But it is not possible to fit an entire ASIC design into a single FPGA device. This problem can be solved by partitioning the given design into multiple small size designs (modules) and fitting those modules into multiple FPGAs. The purpose of my thesis is to take a large RTL (Register Transfer Level) design of an ASIC into consideration, write and test the software ("C" code) practically to synthesize each top level module and analyze the size of each module in terms of number of CLBs (Configurable Logic Blocks), I/Os, flip-flops, latches and apply the algorithm to partition it automatically into minimum number of FPGAs.","abstract_has_math":false,"creators":["Dhavlikar, Nilesh V"],"institution":"University of Nevada, Las Vegas","degree_name":"Master of Science (MS)","degree_level":"Thesis","degree_discipline":"Electrical and Computer Engineering","degree_department":null,"school":null,"contributors":["Henry Selvaraj"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2000,"date_issued":"2000-01-01T08:00:00Z","date_published":"2000-01-01T08:00:00Z","updated_at":"2026-07-24T05:25:18Z","subjects":[],"languages":["English"],"rights":["IN COPYRIGHT. For more information about this rights statement, please visit http://rightsstatements.org/vocab/InC/1.0/"],"rights_urls":[],"identifier_entries":[{"key":"dc:identifier","label":"Identifier","values":["https://oasis.library.unlv.edu/rtds/1240"],"render_values":[{"text":"https://oasis.library.unlv.edu/rtds/1240","href":"https://oasis.library.unlv.edu/rtds/1240","code":true}]}]},"links":{"outbound_url":"https://doi.org/10.25669/jrm5-17mc","outbound_label":"DOI","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Henry Selvaraj"]},{"key":"dc:creator","label":"Author","values":["Dhavlikar, Nilesh V"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:publisher","label":"Institution","values":["University of Nevada, Las Vegas"]},{"key":"dc:type","label":"Dc Type","values":["Text"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical and Computer Engineering"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Thesis"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Master of Science (MS)"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["English"]},{"key":"dc:rights","label":"Dc Rights","values":["IN COPYRIGHT. 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But it is not possible to fit an entire ASIC design into a single FPGA device. This problem can be solved by partitioning the given design into multiple small size designs (modules) and fitting those modules into multiple FPGAs. The purpose of my thesis is to take a large RTL (Register Transfer Level) design of an ASIC into consideration, write and test the software (\"C\" code) practically to synthesize each top level module and analyze the size of each module in terms of number of CLBs (Configurable Logic Blocks), I/Os, flip-flops, latches and apply the algorithm to partition it automatically into minimum number of FPGAs."]},{"key":"dc:format","label":"Dc Format","values":["pdf"]},{"key":"dc:title","label":"Title","values":["Partitioning of large HDL ASIC designs into multiple FPGA devices for prototyping and verification"]}]}],"canonical_facts":{"dc:contributor":["Henry Selvaraj"],"dc:creator":["Dhavlikar, Nilesh V"],"dc:description.abstract":["The ASIC (Application specific Integrated Circuit) designs grow continuously bigger and bigger. This causes dramatic increase in the simulation run time. It is very hard to simulate these designs because the simulation time has risen from hours to days and weeks. Hardware Embedded Simulation (HES) is a technology that facilitates incremental design verification of ASICs. The FPGAs (Field Programmable Gate Arrays) can play an important role in ASIC design cycle. But it is not possible to fit an entire ASIC design into a single FPGA device. This problem can be solved by partitioning the given design into multiple small size designs (modules) and fitting those modules into multiple FPGAs. The purpose of my thesis is to take a large RTL (Register Transfer Level) design of an ASIC into consideration, write and test the software (\"C\" code) practically to synthesize each top level module and analyze the size of each module in terms of number of CLBs (Configurable Logic Blocks), I/Os, flip-flops, latches and apply the algorithm to partition it automatically into minimum number of FPGAs."],"dc:format":["pdf"],"dc:identifier":["10.25669/jrm5-17mc","https://oasis.library.unlv.edu/rtds/1240","https://oasis.library.unlv.edu/context/rtds/article/2239/viewcontent/uc.pdf"],"dc:language":["English"],"dc:publisher":["University of Nevada, Las Vegas"],"dc:rights":["IN COPYRIGHT. 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