Design of a low power switched-capacitor pipeline analog-to-digital converter

<p>An Analog to Digital Converter (ADC) is a circuit which converts an analog signal into digital signal. Real world is analog, and the data processed by the computer or by other signal processing systems is digital. Therefore, the need for ADCs is obvious.</p><p>In this thesis, several novel designs used to improve ADCs operation speed and reduce ADC power consumption are proposed. First, a high speed switched source follower (SSF) sample and hold amplifier without feedthrough penalty is implemented and simulated. The SSF sample and hold amplifier can achieve 6 Bit resolution with sampling rate at 10Gs/s.</p><p>Second, a novel rail-to-rail time domain comparator used in successive approximation register ADC (SAR ADC) is implemented and simulated. The simulation results show that the proposed SAR ADC can only consume 1.3 muW with a 0.7 V power supply.</p><p>Finally, a prototype pipeline ADC is implemented and fabricated in an IBM 90nm CMOS process. The proposed design is validated using measurement on a fabricated silicon IC, and the proposed 10-bit ADC achieves a peak signal-to-noise- and-distortion-ratio (SNDR) of 47 dB. This SNDR translates to a figure of merit (FOM) of 2.6N/conversion-step with a 1.2 V power supply.</p>

Name thesis:degree_name

Doctor of Philosophy

Level thesis:degree_level

Dissertation

Year

2011

Author dc:creator

• Chen, Gang

Contributors dc:contributor

• Kuan Zhou

• Engineering
• Electronics and Electrical

Repository record dc:identifier

https://scholars.unh.edu/dissertation/623

OAI identifier oai:identifier

oai:scholars.unh.edu:dissertation-1622