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University of Minnesota

Efficient on-chip Network architectures for multicore VLSI systems.

Abstract

dc:description.abstract

Designing an efficient and flexible on-chip interconnect structure which can connect a large number of cores is an important issue since continued scaling of semiconductor technologies will enable an ever greater number of cores or processing elements (PEs) to be placed onto a chip. As a result, the Network-on-Chip (NoC) architecture, which provides packet-based routing, is emerging as a solution which can provide a scalable communication platform. In this thesis, we propose a multicasting and bandwidth-reusable Code Division Multiple Access (CDMA) based on-chip switch and demonstrate its capabilities to provide an efficient and error-tolerant NoC architecture. We propose a novel, flexible codeword assignment technique for a CDMA switch. Based on this technique, we propose a comprehensive method for reallocating bandwidth between different PEs on an as-needed basis as well as a low-overhead multicasting technique for CDMA switches. Using this proposed switch, we have simulated a 20-core star topology network. The results show that multicasting and bandwidth reallocation increase the network performance in terms of throughput and latency. Next, a mesh-star hybrid topology with multicasting CDMA switch is introduced. The results show that this approach alleviates the hotspot problem that occurs in a conventional 2D-mesh network and also exhibits a better multicasting performance. In addition, we develop a semi-distributed scheduling method for flexible codeword assignment in a CDMA NoC. This architecture reduces the latency for high injection rate, smallsize packets with a reasonable area cost. We also propose error management strategies for a CDMA switch, and their performance metrics and costs are compared. Finally, we apply the CDMA NoC architecture to the design of a reconfigurable Software Defined Radio (SDR) baseband platform and compared its performance with the conventional 2D-mesh approach.

Author and committee

dc:creator, dc:contributor.*
Author dc:creator
  • Lee, Woojoon

Subjects

dc:subject × 5

Rights

Language dc:language.iso
en_US

Identifiers

dc:identifier.*
Repository record dc:identifier.uri
http://purl.umn.edu/57220
OAI identifier oai:identifier
oai:conservancy.umn.edu:11299/57220

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Last updated
2026-07-24
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citation

Lee, Woojoon. Efficient on-chip Network architectures for multicore VLSI systems.. 2009. http://purl.umn.edu/57220