{"id":{"repo_id":"umn","oai_identifier":"oai:conservancy.umn.edu:11299/57220"},"canonical_url":"https://search.dev.ndltd.org/etd/umn/oai:conservancy.umn.edu:11299/57220","repository":{"repo_id":"umn","name":"University of Minnesota","base_url":"https://conservancy.umn.edu/server/oai/request"},"display":{"title":"Efficient on-chip Network architectures for multicore VLSI systems.","abstract":"Designing an efficient and flexible on-chip interconnect structure which can connect a large number of cores is an important issue since continued scaling of semiconductor technologies will enable an ever greater number of cores or processing elements (PEs) to be placed onto a chip. As a result, the Network-on-Chip (NoC) architecture, which provides packet-based routing, is emerging as a solution which can provide a scalable communication platform. In this thesis, we propose a multicasting and bandwidth-reusable Code Division Multiple Access (CDMA) based on-chip switch and demonstrate its capabilities to provide an efficient and error-tolerant NoC architecture. We propose a novel, flexible codeword assignment technique for a CDMA switch. Based on this technique, we propose a comprehensive method for reallocating bandwidth between different PEs on an as-needed basis as well as a low-overhead multicasting technique for CDMA switches. Using this proposed switch, we have simulated a 20-core star topology network. The results show that multicasting and bandwidth reallocation increase the network performance in terms of throughput and latency. Next, a mesh-star hybrid topology with multicasting CDMA switch is introduced. The results show that this approach alleviates the hotspot problem that occurs in a conventional 2D-mesh network and also exhibits a better multicasting performance. In addition, we develop a semi-distributed scheduling method for flexible codeword assignment in a CDMA NoC. This architecture reduces the latency for high injection rate, smallsize packets with a reasonable area cost. We also propose error management strategies for a CDMA switch, and their performance metrics and costs are compared. Finally, we apply the CDMA NoC architecture to the design of a reconfigurable Software Defined Radio (SDR) baseband platform and compared its performance with the conventional 2D-mesh approach.","abstract_html":"Designing an efficient and flexible on-chip interconnect structure which can connect a large number of cores is an important issue since continued scaling of semiconductor technologies will enable an ever greater number of cores or processing elements (PEs) to be placed onto a chip. As a result, the Network-on-Chip (NoC) architecture, which provides packet-based routing, is emerging as a solution which can provide a scalable communication platform. In this thesis, we propose a multicasting and bandwidth-reusable Code Division Multiple Access (CDMA) based on-chip switch and demonstrate its capabilities to provide an efficient and error-tolerant NoC architecture. We propose a novel, flexible codeword assignment technique for a CDMA switch. Based on this technique, we propose a comprehensive method for reallocating bandwidth between different PEs on an as-needed basis as well as a low-overhead multicasting technique for CDMA switches. Using this proposed switch, we have simulated a 20-core star topology network. The results show that multicasting and bandwidth reallocation increase the network performance in terms of throughput and latency. Next, a mesh-star hybrid topology with multicasting CDMA switch is introduced. The results show that this approach alleviates the hotspot problem that occurs in a conventional 2D-mesh network and also exhibits a better multicasting performance. In addition, we develop a semi-distributed scheduling method for flexible codeword assignment in a CDMA NoC. This architecture reduces the latency for high injection rate, smallsize packets with a reasonable area cost. We also propose error management strategies for a CDMA switch, and their performance metrics and costs are compared. Finally, we apply the CDMA NoC architecture to the design of a reconfigurable Software Defined Radio (SDR) baseband platform and compared its performance with the conventional 2D-mesh approach.","abstract_has_math":false,"creators":["Lee, Woojoon"],"institution":null,"degree_name":null,"degree_level":null,"degree_discipline":null,"degree_department":null,"school":null,"contributors":[],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2009,"date_issued":"2009-10","date_published":"2009-10","updated_at":"2026-07-24T05:19:56Z","subjects":["CDMA","Multicasting","NoC","On-Chip Network","Electrical Engineering"],"languages":["en_US"],"rights":[],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"http://purl.umn.edu/57220","outbound_label":"Repository record","outbound_source":"dc:identifier.uri"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:creator","label":"Author","values":["Lee, Woojoon"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date.accessioned","label":"Dc Date Accessioned","values":["2010-02-04T19:47:38Z"]},{"key":"dc:date.available","label":"Dc Date Available","values":["2010-02-04T19:47:38Z"]},{"key":"dc:date.issued","label":"Date","values":["2009-10"]},{"key":"dc:type","label":"Dc Type","values":["Thesis or Dissertation"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["CDMA","Multicasting","NoC","On-Chip Network","Electrical Engineering"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language.iso","label":"Language (ISO)","values":["en_US"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier.uri","label":"Identifier URI","values":["http://purl.umn.edu/57220"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["University of Minnesot Ph.D. dissertation. October 2009. Major: Electrical Engineering. Advisor: Gerald E. Sobelman. 1 computer file (PDF) x, 89 pages, Ill. (some col.)"]},{"key":"dc:description.abstract","label":"Abstract","values":["Designing an efficient and flexible on-chip interconnect structure which can connect a large number of cores is an important issue since continued scaling of semiconductor technologies will enable an ever greater number of cores or processing elements (PEs) to be placed onto a chip. As a result, the Network-on-Chip (NoC) architecture, which provides packet-based routing, is emerging as a solution which can provide a scalable communication platform. In this thesis, we propose a multicasting and bandwidth-reusable Code Division Multiple Access (CDMA) based on-chip switch and demonstrate its capabilities to provide an efficient and error-tolerant NoC architecture. We propose a novel, flexible codeword assignment technique for a CDMA switch. Based on this technique, we propose a comprehensive method for reallocating bandwidth between different PEs on an as-needed basis as well as a low-overhead multicasting technique for CDMA switches. Using this proposed switch, we have simulated a 20-core star topology network. The results show that multicasting and bandwidth reallocation increase the network performance in terms of throughput and latency. Next, a mesh-star hybrid topology with multicasting CDMA switch is introduced. The results show that this approach alleviates the hotspot problem that occurs in a conventional 2D-mesh network and also exhibits a better multicasting performance. In addition, we develop a semi-distributed scheduling method for flexible codeword assignment in a CDMA NoC. This architecture reduces the latency for high injection rate, smallsize packets with a reasonable area cost. We also propose error management strategies for a CDMA switch, and their performance metrics and costs are compared. Finally, we apply the CDMA NoC architecture to the design of a reconfigurable Software Defined Radio (SDR) baseband platform and compared its performance with the conventional 2D-mesh approach."]},{"key":"dc:title","label":"Title","values":["Efficient on-chip Network architectures for multicore VLSI systems."]}]}],"canonical_facts":{"dc:creator":["Lee, Woojoon"],"dc:date.accessioned":["2010-02-04T19:47:38Z"],"dc:date.available":["2010-02-04T19:47:38Z"],"dc:date.issued":["2009-10"],"dc:description":["University of Minnesot Ph.D. dissertation. October 2009. Major: Electrical Engineering. Advisor: Gerald E. Sobelman. 1 computer file (PDF) x, 89 pages, Ill. (some col.)"],"dc:description.abstract":["Designing an efficient and flexible on-chip interconnect structure which can connect a large number of cores is an important issue since continued scaling of semiconductor technologies will enable an ever greater number of cores or processing elements (PEs) to be placed onto a chip. As a result, the Network-on-Chip (NoC) architecture, which provides packet-based routing, is emerging as a solution which can provide a scalable communication platform. In this thesis, we propose a multicasting and bandwidth-reusable Code Division Multiple Access (CDMA) based on-chip switch and demonstrate its capabilities to provide an efficient and error-tolerant NoC architecture. We propose a novel, flexible codeword assignment technique for a CDMA switch. Based on this technique, we propose a comprehensive method for reallocating bandwidth between different PEs on an as-needed basis as well as a low-overhead multicasting technique for CDMA switches. Using this proposed switch, we have simulated a 20-core star topology network. The results show that multicasting and bandwidth reallocation increase the network performance in terms of throughput and latency. Next, a mesh-star hybrid topology with multicasting CDMA switch is introduced. The results show that this approach alleviates the hotspot problem that occurs in a conventional 2D-mesh network and also exhibits a better multicasting performance. In addition, we develop a semi-distributed scheduling method for flexible codeword assignment in a CDMA NoC. This architecture reduces the latency for high injection rate, smallsize packets with a reasonable area cost. We also propose error management strategies for a CDMA switch, and their performance metrics and costs are compared. Finally, we apply the CDMA NoC architecture to the design of a reconfigurable Software Defined Radio (SDR) baseband platform and compared its performance with the conventional 2D-mesh approach."],"dc:identifier.uri":["http://purl.umn.edu/57220"],"dc:language.iso":["en_US"],"dc:subject":["CDMA","Multicasting","NoC","On-Chip Network","Electrical Engineering"],"dc:title":["Efficient on-chip Network architectures for multicore VLSI systems."],"dc:type":["Thesis or Dissertation"]},"updated_at":"2026-07-24T05:19:56Z"}