Mitigating variability in HPC systems and applications for performance and power efficiency

Power consumption and process variability are two important, interconnected, challenges of future generation large-scale High Performance Computing (HPC) data centers. For example, current production petaflop supercomputers consume more than 10 megawatts of machine and cooling power that costs millions of dollars every year. As HPC moves towards exascale computing, these costs will increase and power consumption is expected to become a major concern. Not solely dynamic behavior of HPC applications but also dynamic behavior of HPC systems makes it challenging to optimize the performance and power efficiency of large scale applications. Dynamic behavior of applications include irregular or imbalanced applications. Dynamic behavior of HPC systems include thermal, power, and frequency variations among processors. Smart and adaptive runtime systems have great potential to handle these challenges transparently from the application. In this dissertation, I first analyze frequency, temperature, and power variations in large- scale HPC systems using thousands of cores and different applications. After I identify the cause of each of these variations, I propose solutions to mitigate these variations to improve performance and power efficiency. When analyzing frequency variation, I attribute manufacturing related intrinsic differences in the chips’ power efficiency as the culprit behind frequency variation under dynamic overclocking. I propose speed-aware dynamic load balancing strategies to mitigate the performance overhead due to frequency variation. When analyzing temperature variation, I focus on inefficiencies in fan-based air cooling systems. I propose proactive and decoupled fan control mechanisms that reduce temperature variations and reduce cooling power consumption by predicting core temperatures using a learning based model. When analyzing power variations, I identify manufacturing related sources of power variation that are static and dynamic. I propose different variation aware node assembly methods to mitigate the power variation. Finally, I propose a fine-grained runtime based technique to mitigate application level variations that are caused by the characteristics of the application itself (for example, applications with different kernel types or phases) in order to reduce the energy consumption.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Computer Science

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2018

Author dc:creator

• Acun, Bilge

Contributors dc:contributor

• Kalé, Laxmikant V
• Abdelzaher, Tarek
• Torrellas, Josep
• Beckman, Pete

• Power
• Energy
• Temperature
• Frequency
• High performance computing (HPC)
• Variability
• Data center
• Performance
• Supercomputer
• Energy consumption
• Power variation
• Frequency variation
• Temperature variation
• Energy efficient algorithms
• Cooling power
• Fan control
• Runtime systems
• Load balancing
• Dynamic runtimes
• Manufacturing variations
• Turbo-boost
• Dynamic voltage and frequency scaling (DVFS)
• Parallel computing

Statement dc:rights

• Copyright 2017 Bilge Acun

Language dc:language

en

Handle dc:identifier

http://hdl.handle.net/2142/99502

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/99502