Evaluation of the practicality of system efficient ESD design

A custom test board facilitates transmission line pulse (TLP) characterization of the external pins of an integrated circuit. Models extracted from the data are used to simulate the pin level response of the integrated circuit (IC) to an IEC 61000-4-2 discharge. Electrostatic discharge (ESD) gun zaps are applied to the test board; simulated and measured waveforms are compared.

Name thesis:degree_name

M.S.

Level thesis:degree_level

Thesis

Discipline thesis:degree_discipline

Electrical & Computer Engr

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2018

Author dc:creator

• Reiman, Chloe Michelle

Contributors dc:contributor

• Rosenbaum, Elyse

• System-efficient electrostatic discharge (ESD) design (SEED)
• System
• Efficient
• Design
• Electrostatic discharge (ESD)
• Electrostatic
• Discharge
• Transmission line pulse (TLP)
• Transmission
• Line
• Pulse

Statement dc:rights

• Copyright 2017 Chloe Michelle Reiman

Language dc:language

eng

Handle dc:identifier

http://hdl.handle.net/2142/99289

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/99289