Next-generation safety-critical systems on multi-core platforms

Multi-core platforms represent the answer of the industry to the increasing demand for computational capabilities. In fact, multi-core platforms can deliver large computational power together with minimum costs, compact size, weight and power usage. Multi-core architectures however are shaking the very foundation of modern real-time computing theory, i.e. the assumption that worst case execution time (WCET) can be calculated on individual tasks to compute the schedulability of the complete system when tasks are running together. This fundamental assumption has been broadly accepted by classic scheduling theory for the past three decades; unfortunately, it is not even true in an approximate sense in a modern multi-core chip, and this leads to a lack of composability. Shared hardware resources like caches, main memory, and I/O buses are all sources of unpredictable timing behavior and temporal dependencies among real-time tasks running in parallel. As a result, certifying systems deployed using multi-core platforms is significantly more challenging compared to single-core implementations. In this work, we tackle the challenge of restoring the constant WCET assumption for real-time tasks deployed on multi-core systems. While predictability and performance determinism are of paramount importance in safety-critical applications, cost containment and time-to-market are dominant factors for the large-scale adoption of novel technologies. Hence, our work proposes solutions that can be adopted with commercially available components, also known as commercial-off-the-shelf (COTS) components. In order to achieve deterministic performance on COTS multi-core platforms, we propose software-level techniques to enforce usage control over shared hardware resources. We also demonstrate that when proper enforcement is performed, real-time analysis can be carried out efficiently. We focus our attention on two main multi-core architectural paradigms: cache-based and scratchpad-based platforms. On multi-core cache-based architectures, we design, implement and analyse a set of OS-level techniques that enforce hardware resource partitioning. In this context, we set two main goals. Our first objective is to achieve strong inter-core performance isolation in spite of inherent hardware resource sharing. On the other hand, our techniques are designed to remain transparent from an application perspective. This requirement allows for minimum re-engineering being required to port legacy single-core systems on multi-core platforms partitioned with the proposed techniques. On scratchpad-based platforms, we follow a different approach. In fact, we propose a redesign of the OS-level scheduling strategies. The goal is to include scratchpad space scheduling, as well as shared memory bus access, together with traditional processor time scheduling. The resulting resource co-scheduling strategy introduces a set of new challenges compared to processor-only scheduling. Nonetheless, it allows to significantly mitigate the problem of inter-core performance interference, as we describe in our evaluations.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Computer Science

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2017

Author dc:creator

• Mancuso, Renato

Contributors dc:contributor

• Caccamo, Marco
• Sha, Lui
• Abdelzaher, Tarek F.
• Brandenburg, Björn

• Real-time systems
• Multi-core systems
• Commercial-off-the-shelf (COTS)
• Single-core equivalence
• Single-core equivalent
• Hardware resource management
• Operating system (OS)
• Real-time operating system (RTOS)
• Worst case execution time (WCET)
• Scheduling
• Schedulability analysis
• Multi-core real-time operating system (RTOS)
• Profiling
• Avionics
• Safety-critical
• Cyber-physical systems (CPS)
• Memguard
• Colored lockdown
• Palloc
• Kernel verification
• Scratchpad-centric operating system (OS)
• Scratchpad memories operating system (SPM-OS)
• Scratchpad scheduling
• Direct memory access (DMA) scheduling
• Flow-shop task
• Flow-shop scheduling
• Hardware scheduler
• Field-programmable gate array (FPGA) scheduler
• Real-time Linux
• Automotive
• Smart manufacturing
• Real-time networking
• Embedded systems
• Multi-core avionics
• Multi-core automotive
• Self-driving cars
• Multi-core safety-critical
• Many-core
• Reconfigurable computing
• Internet of things
• Real-time cloud computing
• Provably safe cyber-physical systems (CPS)
• Multi-core scheduling
• Performance isolation
• Real-time resource management
• Real-time cache
• Real-time dynamic random access memory (DRAM)
• P4080
• MPC5777M
• Inter-core interference
• Interference channels
• CAST32
• CAST32A
• Federal Aviation Administration (FAA)
• Minimal multicore avionics certification guidance
• Multi-core automotive open system architecture (AUTOSAR)
• DO-178C
• DO-178B
• Resource partitioning
• Multi-core resource partitioning
• Predictable execution model (PREM)
• Multi-core predictable execution model (PREM)

Statement dc:rights

• Copyright 2017 Renato Mancuso

Language dc:language

en

Handle dc:identifier

http://hdl.handle.net/2142/97399

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/97399