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University of Illinois at Urbana-Champaign

Opportunistic power reassignment between processor and memory in 3D stacks

Abstract

dc:description

The pin count largely determines the cost of a chip package, which is often comparable to the cost of a die. In 3D processor-memory designs, power and ground (P/G) pins can account for the majority of the pins. This is because packages include separate pins for the disjoint processor and memory power delivery networks (PDNs). Supporting separate PDNs and P/G pins for processor and memory is inefficient, as each set has to be provisioned for the worst-case power delivery requirements. In this thesis, we propose to reduce the number of P/G pins of both processor and memory in a 3D design, and dynamically and opportunistically divert some power between the two PDNs on demand. To perform the power transfer, we use a small bidirectional on-chip voltage regulator that connects the two PDNs. Our concept, called Snatch, is effective. It allows the computer to execute code sections with high processor or memory power requirements without having to throttle performance. We evaluate Snatch with simulations of an 8-core multicore stacked with two memory dies. In a set of compute-intensive codes, the processor snatches memory power for 30% of the time on average, speeding-up the codes by up to 23% over advanced turbo-boosting; in memory-intensive codes, the memory snatches processor power. Alternatively, Snatch can reduce the package cost by about 30%.

Degree

thesis:*
Name thesis:degree_name
M.S.
Level thesis:degree_level
Thesis
Discipline thesis:degree_discipline
Computer Science
Grantor
University of Illinois at Urbana-Champaign
Year dc:date
2017

Author and committee

dc:creator, dc:contributor.*
Author dc:creator
  • Skarlatos, Dimitrios State
Contributors dc:contributor
  • Torrellas, Josep

Subjects

dc:subject × 9

Rights

dc:rights
Statement dc:rights
  • Copyright 2016 Dimitrios Skarlatos
Language dc:language
en

Identifiers

dc:identifier.*
Handle dc:identifier
http://hdl.handle.net/2142/95609
OAI identifier oai:identifier
oai:www.ideals.illinois.edu:2142/95609

Chain of custody

source
Harvested from
University of Illinois - Urbana-Champaign
Base URL
www.ideals.illinois.edu/oai-pmh
Last updated
2026-07-22
Source record
OAI-PMH GetRecord
citation

Skarlatos, Dimitrios State. Opportunistic power reassignment between processor and memory in 3D stacks. Thesis thesis, University of Illinois at Urbana-Champaign, 2017. http://hdl.handle.net/2142/95609