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University of Illinois at Urbana-Champaign
Power Estimation and Minimization of Digital Signal Processing Systems
Abstract
dc:descriptionWe have so far focussed on power dissipation in static CMOS circuits. Dynamic logic circuits are used in high-performance circuits due to their speed and area advantage over static CMOS circuits. In this thesis, we also present an optimization technique, termed clock-generating (CG) domino, for dual-output domino logic that reduces area, dock load, and power without increasing the delay. A delayed clock, generated from certain dual-output gates, is used to convert other dual-output gates to single output.
Degree
thesis:*- Name thesis:degree_name
- Ph.D.
- Level thesis:degree_level
- Dissertation
- Discipline thesis:degree_discipline
- Computer Science
- Grantor
- University of Illinois at Urbana-Champaign
- Year dc:date
- 2015
Author and committee
dc:creator, dc:contributor.*- Author dc:creator
-
- Ramprasad, Sumant
- Contributors dc:contributor
-
- Naresh Shanbhag
- Ibrahim Hajj
Subjects
dc:subject × 1Rights
- Language dc:language
- eng
Identifiers
dc:identifier.*- Identifier
- (MiAaPQ)AAI9944976
- OAI identifier oai:identifier
- oai:www.ideals.illinois.edu:2142/81947