Parallel Algorithms for VHDL Simulation

We finally settled on a partitioning based approach to parallelization. This technique gives us acceptable speedups, if the partitioning and placement of partitions on processors is done carefully. Partitioning and placement issues are examined thoroughly in this thesis.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Computer Science

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2015

Author dc:creator

• Krishnaswamy, Venkatram

Contributors dc:contributor

• Banerjee, Prithviraj

• Engineering, Electronics and Electrical

Language dc:language

eng

Identifier

(MiAaPQ)AAI9737169

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/81882