Tradeoffs in Designing Massively Parallel Accelerator Architectures

We propose a methodology for performing an integrated optimization of both the micro-architecture and the physical circuit design of the cores and caches. In our approach, we use statistical sampling of the design space for evaluating the performance of the micro-architecture and RTL synthesis to characterize the area-power-delay of the underlying circuits. This integrated methodology enables a much more powerful analysis of the performance-area and performance-power tradeoffs for the low level micro-architecture. We use this methodology to find the optimal design points for an accelerator architecture under area constraints and power constraints. Our results indicate that more complex architectures scale well in terms of performance per area, but that the addition of a power constraint favors simpler architectures.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Computer Science

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2015

Author dc:creator

• Mahesri, Aqeel A.

Contributors dc:contributor

• Patel, Sanjay J.

• Computer Science

Language dc:language

eng

Identifier

(MiAaPQ)AAI3363030

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/81853