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University of Illinois at Urbana-Champaign
Architectural Techniques to Mitigate the Effect of Spatial and Temporal Variations in Processors
Abstract
dc:descriptionTo address this problem, we show how to hide the effects of aging and slow it down. Our framework is called Facelift. It hides aging through aging-driven application scheduling. It slows down aging by applying voltage changes at key times---it uses a non-linear optimization algorithm to carefully balance the impact on the aging rate and on the critical path delays. Moreover, it can gainfully configure the chip for a short lifetime. We can take a multicore with a 7-year lifetime and, by hiding and slowing down aging, enable it to cycle, on average, at a 14--15% higher frequency. Alternatively, we can design a multicore for a 5 to 7-month lifetime and use it for 7 years.
Degree
thesis:*- Name thesis:degree_name
- Ph.D.
- Level thesis:degree_level
- Dissertation
- Discipline thesis:degree_discipline
- Computer Science
- Grantor
- University of Illinois at Urbana-Champaign
- Year dc:date
- 2015
Author and committee
dc:creator, dc:contributor.*- Author dc:creator
-
- Tiwari, Abhishek
- Contributors dc:contributor
-
- Torrellas, Josep
Subjects
dc:subject × 1Rights
- Language dc:language
- eng
Identifiers
dc:identifier.*- Identifier
- (MiAaPQ)AAI3337941
- OAI identifier oai:identifier
- oai:www.ideals.illinois.edu:2142/81837