Techniques to Mitigate the Effects of Congenital Faults in Processors

Using this model we introduce a novel framework that shows how microarchitecture techniques can mitigate variation-induced errors and even trade them off for power and processor frequency. Several such techniques are analyzed---in particular, a high-dimensional dynamic-adaptation technique that maximizes performance when there is slack in variation-induced error rate and power. The results show that our best combination of techniques increases processor frequency by 61% on average, allowing the processor to cycle 26% faster than without variation. Processor performance increases by 44% on average, resulting in a performance that is 18% higher than without variation---at only a 12.5% area cost.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Computer Science

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2015

Author dc:creator

• Sarangi, Smruti R.

Contributors dc:contributor

• Torrellas, Josep

• Computer Science

Language dc:language

eng

Identifier

(MiAaPQ)AAI3270016

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/81768