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University of Illinois at Urbana-Champaign

Chip Multiprocessors With Speculative Multithreading: Design for Performance and Energy Efficiency

Abstract

dc:description

Experiments with the SpecInt 2000 codes show that a CMP with 4 3-issue cores and support for SM delivers a speedup of 1.27 over a 3-issue superscalar. The SM CMP is even faster than a 6-issue superscalar at the same frequency, and consumes only 85% of its power. In fact, for the same average power in both chips, the SM CMP is 1.13 times faster than the 6-issue superscalar on average.

Degree

thesis:*
Name thesis:degree_name
Ph.D.
Level thesis:degree_level
Dissertation
Discipline thesis:degree_discipline
Computer Science
Grantor
University of Illinois at Urbana-Champaign
Year dc:date
2015

Author and committee

dc:creator, dc:contributor.*
Author dc:creator
  • Renau, Jose
Contributors dc:contributor
  • Torrellas, Josep

Subjects

dc:subject × 1

Rights

Language dc:language
eng

Identifiers

dc:identifier.*
Identifier
(MiAaPQ)AAI3153411
OAI identifier oai:identifier
oai:www.ideals.illinois.edu:2142/81651

Chain of custody

source
Harvested from
University of Illinois - Urbana-Champaign
Base URL
www.ideals.illinois.edu/oai-pmh
Last updated
2026-07-22
Source record
OAI-PMH GetRecord
citation

Renau, Jose. Chip Multiprocessors With Speculative Multithreading: Design for Performance and Energy Efficiency. Dissertation thesis, University of Illinois at Urbana-Champaign, 2015. http://hdl.handle.net/2142/81651