Multi-Bit Delta -Sigma Modulation Technique for Fractional-N Frequency Synthesizers

This thesis proposes a multi-bit Delta-Sigma modulation technique as a spur reduction method to enhance the overall synthesizer performance, and the oversampling modulator performance is analyzed with the consideration of practical design aspects for frequency synthesizers. A prototype fractional- N frequency synthesizer using a 3-b third-order Delta-Sigma modulator has been designed and implemented in 0.5-gm CMOS. Synthesizing 900 MHz with 1-Hz resolution, it exhibits an in-band phase noise of --92 dBc/Hz at 10-kHz offset with a reference spur of less than --95 dBc. Experimental results show that the proposed system is applicable to low-cost, low-power wireless applications and that it meets the requirements of most RF applications including multi-slot GSM, IS-54, CDMA, and PDC.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Electrical Engineering

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2015

Author dc:creator

• Rhee, Woogeun

Contributors dc:contributor

• Song, Bang-Sup

• Engineering, Electronics and Electrical

Language dc:language

eng

Identifier

(MiAaPQ)AAI9996677

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/81372