Architectural and Compiler Techniques for Energy Reduction in High-Performance Microprocessors

More specifically, we propose a technique that uses an additional mini cache located between the instruction cache (I-Cache) and the CPU core; the mini cache buffers instructions that are nested within loops and are continuously fetched from the I-Cache. This mechanism can create very substantial energy savings, since the I-Cache unit is one of the main power consumers in most of today's high-performance microprocessors. Results are reported for the SPEC95 benchmarks in the R-4400 processor which implements the MIPS2 instruction set architecture.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Electrical Engineering

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2015

Author dc:creator

• Bellas, Nikolaos

Contributors dc:contributor

• Ibrahim Hajj

• Energy

Language dc:language

eng

Identifier

(MiAaPQ)AAI9921661

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/81278