Run-Time Adaptive Cache Management

The objective of this dissertation is to improve cache effectiveness, taking advantage of the growing chip area, utilizing run-time adaptive cache management techniques, and optimizing both performance and cost of implementation. Specifically, the aim is to increase cache effectiveness for integer programs. This dissertation proposes a microarchitecture scheme where the hardware determines data placement within the cache hierarchy based on dynamic referencing behavior. This scheme is fully compatible with existing instruction set architectures. This dissertation also examines the theoretical upper bounds on the cache hit ratio that the proposed techniques can provide, for several integer applications. Then, detailed trace-driven simulations of several integer applications are used to show that the implementations described in this dissertation can achieve performance close to that of the upper bound.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Electrical Engineering

Grantor

University of Illinois at Urbana-Champaign

Date dc:date

10000-01-01

Author dc:creator

• Johnson, Teresa Louise

Contributors dc:contributor

• Hwu, Wen-Mei W.

• Computer Science

Language dc:language

eng

Identifier

(MiAaPQ)AAI9904493

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/81247