Dynamic Rate Controlled Input -Buffered Switch System With QoS

In the dissertation, we propose a new scheduling algorithm, dynamic rate controlled input output (DRCIO), which addresses the scalability and the implementability for a highly distributed high speed router. We developed the algorithm based on a Washington University (WASU) high speed switch. We first review the relationship between the queuing mechanism and the scheduling algorithm. We discuss the importance of the proper queuing mechanism for a router to be scalable. And we explain the in detail the measurement based backlog estimation for the distributed packet scheduling algorithm. We show that the complexity of this method is O(1) to calculate the total backlog, which is a significant improvement as it normally takes O( V), where V is the number of flows in a router. We also review the risks of inaccuracy when we resort to this O( 1) method. To prove the robustness of the DRCIO, we review the operation of the DRCIO in several boundary conditions, and show that the algorithm is robust enough to recover from any boundary or erroneous conditions.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Electrical Engineering

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2015

Author dc:creator

• Park, Sueng-Yong

Contributors dc:contributor

• Steve (sung-Mo) Kong

• Engineering, Electronics and Electrical

Language dc:language

eng

Identifier

(MiAaPQ)AAI3160938

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/80896