Algorithms and Architectures for Joint Equalization and Decoding

Various linear turbo equalizer VLSI architectures are explored. Energy-efficient architectures that eliminate redundant operations and employing early termination achieve power savings up to 60%. To improve the throughput, a concurrent processing VLSI architecture is proposed, where SISO equalizers and decoders are running concurrently, thereby increasing throughput by up to 75%. To improve the BER further, a class of switching linear turbo equalizers is also shown along with several feasible switching schemes.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Electrical Engineering

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2015

Author dc:creator

• Lee, Seok-Jun

Contributors dc:contributor

• Shanbhag, Naresh R.
• Singer, Andrew C.

• Engineering, Electronics and Electrical

Language dc:language

eng

Identifier

(MiAaPQ)AAI3160911

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/80893