Power Distribution Network Analysis and Optimization in Digital VLSI Circuits

We propose a novel approach to the analysis and design of reliable power distribution networks for digital VLSI circuits. The optimized power and ground buses should meet or outperform the noise level specifications while achieving minimum die size. The flow consists of two main steps: analysis and optimization. During the analysis phase, the power and ground buses are broken down into multilevel hierarchical structures. Different algorithms are employed for the analysis at different hierarchies. In all the analyses, input-independent algorithms are used to reduce simulation time and obtain an accurate noise upper bound. Additional techniques (namely, sensitivity analysis, constraint graph optimization, and reduced order modeling techniques) are also employed to improve the accuracy with little overhead in terms of the simulation time. An algorithm is developed to determine the conditions that will cause maximum delay along target critical paths with power/ground bus voltage variation effects. Finally, new techniques for decoupling capacitance placement and power grid area optimization are presented.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Electrical Engineering

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2015

Author dc:creator

• Bai, Geng

Contributors dc:contributor

• Hajj, Ibrahim N.

• Engineering, Electronics and Electrical

Language dc:language

eng

Identifier

(MiAaPQ)AAI3130874

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/80853