VLSI Architectures for Iterative Channel Decoders

Decoder architectures for LDPC codes introduce another complexity dimension related to the on-chip interconnect bottleneck of LDPC decoders. A new parameterized-core-based design methodology targeted for scalable and programmable LDPC decoders is proposed. The methodology solves the problems of excessive memory overhead, high latency, and complex on-chip interconnect typical of existing decoder implementations, which limit the scalability, degrade the error-correction capability, and restrict the domain of application of LDPC codes. Diverse memory and interconnect optimizations are performed at the code-design, decoding algorithm, decoder architecture, and physical layout levels. The methodology proposes: (1) The concept of architecture-aware LDPC code design that solves the interconnect bottleneck, (2) a faster and memory-efficient turbo-decoding algorithm for LDPC codes, and a reduced-complexity mechanism for message computations, (3) a programmable, scalable, and code-rate tunable architecture platform, and (4) a core-generator for high performance decoders. A decoder chip has been implemented using this methodology in 0.18 mum technology, which delivers a throughput of 1.6 Gbps at 125 MHz and consumes 760 mW of power.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Electrical Engineering

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2015

Author dc:creator

• Mansour, Mohammad Monzer

Contributors dc:contributor

• Shanbhag, Naresh R.

• Engineering, Electronics and Electrical

Language dc:language

eng

Identifier

(MiAaPQ)AAI3086131

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/80824