Run -Time Optimization Architecture

This thesis presents a hardware mechanism for generating and deploying run-time optimized code. The system exploits program execution phasing by automatically detecting and optimizing the instruction sequences that comprise the phase, called a hot spot. The hardware mechanism can be viewed as a filtering system that resides after the retirement stage of the processor pipeline, accepts an instruction execution stream as input, and produces instruction profiles and sets of linked, optimized traces as output. The code deployment mechanism uses an extension to the branch prediction mechanism to migrate execution into the new code without modifying the original code. These new components do not add delay to the execution of the program except during short bursts of reoptimization, because they operate in parallel with native execution. This technique provides a strong platform for run-time optimization because the hot execution regions are extracted, optimized, and written to main memory for execution where they will persist across context switches. The framework is designed to preserve precise exception handling while applying optimizations which currently include partial function in-lining (even into shared libraries), code straightening, loop unrolling, peephole optimizations, and instruction rescheduling with renaming, which are all concurrently performed with the running application.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Electrical Engineering

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2015

Author dc:creator

• Merten, Matthew Carl

Contributors dc:contributor

• Hwu, Wen-Mei W.

• Engineering, Electronics and Electrical

Language dc:language

eng

Identifier

(MiAaPQ)AAI3070388

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/80800