Reliable and Low -Power Signal Processing via Algorithmic Noise -Tolerance

In this dissertation, we address the problem of designing reliable and low-power VLSI systems for communications and DSP applications. An information theoretic framework to derive the lower bound on energy dissipation of VLSI circuits in presence of deep submicron noise is presented. It is shown that error-control coding can be employed to approach these bounds. We introduce algorithmic noise-tolerance (ANT) which is employing error-control at the algorithmic level to achieve reliable operation in presence of noise. We introduce voltage overscaling where the supply voltage is reduced beyond the limit imposed by the critical path delay to reduce energy dissipation. The resulting degradation in algorithmic performance is restored by employing ANT, thereby achieving energy savings while meeting the algorithmic performance specifications.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Electrical and Computer Engineering

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2015

Author dc:creator

• Hegde, Rajamohana M.

Contributors dc:contributor

• Shanbhag, Naresh R.

• Engineering, Electronics and Electrical

Language dc:language

eng

Identifier

(MiAaPQ)AAI3044109

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/80762