High-Speed, Low-Spurious CMOS Analog -to -Digital Converter

Pipelining not only provides a speed advantage, but also enables the application of background offset trimming to folding ADCs. Background offset trimming with a delta-sigma modulator is applied to compensate the random input offset of folding amplifiers. A subranging front-end is used in conjunction with the pipelined folding ADC to make the calibration feasible. The second prototype chip was measured to exhibit 40 Msamples/s conversion rate with 13-bit resolution, consuming 800 mW at 5 V.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Electrical Engineering

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2015

Author dc:creator

• Choe, Myung-Jun

Contributors dc:contributor

• Song, Bang-Sup

• Engineering, Electronics and Electrical

Language dc:language

eng

Identifier

(MiAaPQ)AAI3030420

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/80747