Design of Energy Efficient SOC With PIM Architecture and Deep Submicron Circuit Techniques

To tackle problems such as tremendously increased leakage current and power consumption due to the scaled threshold voltage of the transistor and increased number of gates in future VLSI chips, sub-1-V circuit techniques to suppress leakage current while meeting performance requirement are developed. High efficient charge recycling logic using charge sharing in the precharge cycle with no pre-evaluation problems and using ac power clocks with bootstrapped NMOS transistors are designed to reduce active power consumption further.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Electrical Engineering

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2015

Author dc:creator

• Yoo, Seung-Moon

Contributors dc:contributor

• Kang, Sung-Mo (Steve)
• Torrellas, Josep

• Engineering, Electronics and Electrical

Language dc:language

eng

Identifier

(MiAaPQ)AAI3023242

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/80745