Systematically controlling the error rates in variation-prone networks-on-chip for energy efficiency

Networks-on-Chip (NoCs) are prone to within-die process variation as they span the whole chip. To tolerate variation, their voltages (Vdd) carry overprovisioned guardbands. As a result, prior work has proposed to save energy by dynamically managing Vdd, operating at reduced Vdd while occasionally su ering and xing errors. Unfortunately, these proposals use ad-hoc controller designs that may not work under other scenarios and do not provide error bounds. This thesis develops a scheme that dynamically minimizes the Vdd of groups of routers in a variation-prone NoC using formal control-theory methods. The scheme, called Contra, saves substantial energy while guaranteeing the stability and convergence of error rates. Moreover, the scheme is enhanced with a low-cost secondary network that retransmits erroneous packets for higher energy e ciency. The enhanced scheme is called Contra+. Both Contra and Contra+ are evaluated using simulations of NoCs with 64{100 routers. In an NoC with 8 routers per Vdd domain, the proposed schemes reduce the average energy consumption of the NoC by 27%; in a futuristic NoC with one router per Vdd domain, Contra+ and Contra reduce the average energy consumption by 37% and 32%, respectively. The performance impact is negligible. These savings are signi cant over the state-of-the-art. The results categorically state that formal control is essential to attain a stable, scalable, and energy-efficient design. Additionally, it is found that while the secondary network helps Contra+ attain higher energy savings, it has a nonnegligible hardware cost. Hence, Contra is the most cost-effective design.

Name thesis:degree_name

M.S.

Level thesis:degree_level

Thesis

Discipline thesis:degree_discipline

Computer Science

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2015

Author dc:creator

• Pothukuchi, Raghavendra Pradyumna

Contributors dc:contributor

• Torrellas, Josep

• Computer Architecture
• Reliability
• Energy efficiency

Statement dc:rights

• Copyright 2014 Raghavendra Pradyumna Pothukuchi

Language dc:language

en

Handle dc:identifier

http://hdl.handle.net/2142/73090

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/73090