Systematic Computer Architecture Prototyping

The current design process for workstation systems is over-taxed due to the size and diversity of realistic workload models. This thesis advocates a method to improve the design process by synthesizing prototype architectures from workloads. Focus is placed on the processor and memory systems, although the overall philosophy is applicable to other workstation components as well. Prototyping of memory systems is performed using methods to evaluate multiple designs with one pass over the address trace. Statistical sampling of address traces is adapted from traditional cache simulation to improve the performance and trace-size range of the techniques. These methods are extended to account for performance penalties due to multiprogramming. Prototyping of superscalar processors is performed using new statistical sampling techniques in conjunction with two simulation algorithms. The resource usage in an unlimited-resource simulation is used to select processor resource needs, but is only applicable to fixed operation latencies. A more general solution based on simulated annealing is developed and demonstrated as a prototyping method. The interaction between prototypes is investigated via simulation of three common schemes for coupling the processor to the memory system: blocking on a cache miss, limited-blocking, and non-blocking. It is concluded that sufficient design options exist to justify the separate design of the processor and the memory.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Electrical Engineering

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2014

Author dc:creator

• Conte, Thomas M.

Contributors dc:contributor

• Hwu, Wen-Mei W.

• Engineering, Electronics and Electrical
• Computer Science

Identifier

(UMI)AAI9305495

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/71978